LMARV-1: A RISC-V processor you can see. Part 1: 32-bit registers.
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- Опубликовано: 14 июл 2024
- The LMARV-1 (Learn Me A Risc-V, version 1) is a RISC-V processor built out of MSI and LSI chips. You can point to pieces of the processor and see the data flow. It should be a nice way of demonstrating how RISC-V works and how simple it is to implement.
RISC-V specs: riscv.org/specifications/
Github for KiCAD schematics and gerbers: github.com/RobertBaruch/lmarv
RISC-V RUclips channel: / @riscvinternational 
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This is one of the clearest explanations of this stuff I've ever seen. Wish I'd had this in my logic design class in college. We did the FPGA RISC impl thing he talks about, and it took way more work to understand than it would have if I'd had this.
Indeed, this is a super informative video. Many thanks!!
it's always good to know the basics, the elements that make up the whole. implementing a processor in fpga is to difficult (at least for me) if i don't understand the basic building blocks. also understanding the sum of its parts gives you the power to work with it debug it, understand it.
Best introduction RISC-V I've seen. Looking forward to seeing next steps! Thanks!
I just finished a computer architecture class focused on RISC-V, I look forward to watching through this series!
"These are the kind that you sprinkle on a printed circuit board to appease the gods"
I feel ya, man, I feel ya.
Also I FEEL that right left confusion. I can drive, but I have to move my hands if I'm using GPS navigation. I know which hand is right by the way it moves when I move my right hand, but I can never remember which direction it is.
Twitter brought me to one of your video where you revese-engineer a quand NAND cmos chip from it's die shot. But this project is much more interesting to me. Subcribed for that and can't wait to see the beast complete! It's awesome to have an open ISA like RISC-V to play with
Awesome. Looking forward to the finished product!
subscribed, can't wait for the rest of the series
Nathaniel Lewis Same for me :D
Subscribed immediately. Really stoked for the next part.
Love this series. You're a great teacher. Looking forward to a discrete components -based RISC-V.
Can't wait for the rest of this series! Very clearly explained.
Excellent video. So excited for the rest of the series!
Great video. Looking forward to part 2.
Great, please continue on this!
That's an awesome project! Subscribed, I don't want to miss that!
Brother, subscribed just after this video to see you take this project to completion, I once designed an 8 bit system, you just inspired me to take that to a whole new level, thanks.
Excellent video. Informative. interesting and a classic example of: Must See TV 👍😁 Thank you.
Thank you for the video cleared up a lot I didn't know about riscv
Great explanation. And with gerbers for grabs! Thank you
Subbed and looking forward to the series. Thank you.
29:56 MOLESMELL, the #1 name in LEDs
Loved it, awesome project and awesome video, can't wait to see the next one.
I've watched a few videos in this genre, (breadboard Z-80, reverse engineering a 6502, etc) and it always amazes me just how simple computers are at their very core. Just flipping, holding, and shifting some bits around to get everything we do on computers today. And yeah, I know this particular RISC-V CPU will be the simplest possible RISC-V, but more advanced versions are really just more of the same thing, arranged in more complex ways.
@Robert Baruch Thank you for sharing your invaluable knowledge.
Really good video, well thought out and delivered. Great information.
Awesome, im glad I found your channel. This and reverse engineering chips has earned you a sub
Subd. Can't wait to see how this turns out!
Great video. With only basic knowledge of processor design you explained everything clearly!
Love your explanation and salute to your efforts ✨👌👌
Thanks For sharing
Interesting project. I've had some success reducing left-right confusion/dyslexia by turning things 90 degrees and thinking about it as up/down.
That's an interesting idea, I'll have to try that!
Interesting. I was thinking computers operate by magic. I'm now thinking computers do not operate by magic at all! Good job!
Q this is why I'm here
Great video(s), interesting project(s), subscribed :D Btw, thanks a lot, now I know I'm not alone with the left/right problem I'm often criticised for ...
at 29:45: sorry to be the guy pointing out to little mistakes.
it's more or less 0.87mA. (3.3V-2V)/1.5k = 0.87mA. The red LED has about 2V for my calculations.
who cares...
Yes, the resistors should be about 150 ohms for 3.3v logic and red LEDs that have a Vf of around 1.5 volts (3.3 - 1.5)/.01 = 160, but 150 is the closest standard value at 5% tolerance. A 1.5 kilohm resistor won’t pass enough current to light the LEDs, or they’ll be so dim that you can only see them with lights out. 😬
Sprinkling some 0.1uF capacitors on the PCBs to please the gods! That one got me!
you explain very well and this I really appreciate.
Yet another idea for source registers configuration might be to use a single bus rather than two, such as by either loading two temporary source registers sequentially, or loading a single temporary register with one source and then using the second source directly from the bus. This might reduce chip count but at the expense of more complex instruction decoding/control signal generation and more clock cycles → slower execution.
I think an important part of the approach is to opt for less complexity in the trade-off between nr of parts/busses and complexity. In practice that means you throw in a lot (!) of bus drivers - but all the same - and get far simpler decoding logic in return. Also note that this way the nr of registers doesn't matter so much, so you can have lots of them.
The basic theme is: "gain modularity (extensibility) by keeping things simple/uniform".
love your videos!
Awesome project!
fantastic explanations !
Took me 1min to sub. These videos are so good
I think you should make the "which output is on" LEDs different color (like green&blue), so that one can easily see which register is used as OP1 and OP2.
Hey hey! Just found the channel and glad i did. Howdy fellow processor nerds!! :D
It's kind of funny how fashionable vintage electronics is these days. Playing with discrete TLL ICs was my hobby in the late 1980s. Other channels show 6502 projects, which was the CPU on my Apple ][ at that time. Well - progress is visible - back then we used to hand wire the pcbs or use FeCl3 acid baths... now it is just mail order :)
Impressive. I want to know more about it !
At first, I thought you were crazy. Now, I love that you're crazy. Sub'd.
Just the *right* kind of crazy :-)
Risky project, but I'll definitely follow this one !
The term of art for those “nubbins” is “mouse bites,” FYI.
Thanks for this. More plz :D
That was a great intro
You are powerful, thanks for your video
Love your videos, keep up the good work....there's going to be lot's of blinky lights here, maybe it will end up looking like the CM-4 or 5 (Thinking Machines Corp.) Just on a smaller scale
Any idea of what clock speed you will aim for, or will you just see what limits you hit once built?
Fascinating project. I wonder why not using 1206 SMD LEDs? Since you use the reflow oven that would spare you hours of soldering through-hole LEDs, not mentioning the fitting issues on PCB.
Oh please disregard my question. I noticed that in later revisions you already did smd LEDs. They look gorgeous!
The HASL finish might bite you if your PCIe sockets are gold plated. You will likely get galvanic / dissimilar metal corrosion over time - I've experienced it a long time ago with Socket-370 to Slot-1 adapter which had a HASL finished. I had to clean it every couple weeks, until I switched to a gold finish adapter.
The thought of soldering all those LED's is making me cry. I used AllPcb in December for a retro project. Definitely some confusion communicating with them but I'm happy I settled with them. I bought 5 boards but got 11 - they were pretty large boards too. Lol
Looking forward to following the project.
They're not bad, I just got frustrated with the amount of questions I was getting from them. And not only on this project.
Be glad you're not the poor sod who ordered 11 and got 5 :D
I'm so excited for this project, can't wait to see the CPU working and "blinking"! Do you plan on running Linux on it, after you finish testing? That would be amazing. RISC-V has Linux builds obviously.
My guess he wont i meen i think hes going for a basic system nothing complex
You need a LOT more to run something like linux
oh cool! you’re using my favorite pen brand!
Brilliant!
This is awesome
am I the only one that gets excited about receiving PCBs in the mail?
😉
Cool project. Hope you don’t regret the HASL fingers on the PCIe card edge.
A DIY gold plating is always possible, I guess.
"These are the .1uF caps that you sprinkle on the PCB or appease the Gods" hahahaha brilliant!
Amazing.
Shades of Woz's Sweet16 implementation on the 6502!
awesome subscribed, i am your new processor friend.
Subscribed
Hi i away wanted to learn how CPU work internally will watch all your episodes will be nice if you make something like paid course and people to be able to learn online !
"Green oil" is Chinese for solder mask. They were probably talking about keeping solder mask between IC pads and edge connector fingers. Seriously, this is such a common thing that they should have learned a proper term of art by now.
Alex Taradov that's what I thought at first, but when I made that change, they came back with the exact same questions. Eventually I determined that "bridge" referred to bridging over the vias. Also, if you Google for "green oil bridge", they seem to use that translated term a lot.
Alex Taradov actually, you are right. It was the solder mask between pads. But everything they asked me seemed to imply tented vias.
Some time ago I did an experiment and ordered the same board from a number of budget manufacturers. Only AllPcb asked this question, which created a lot of confusion. The rest just silently removed everything they could not manufacture reliably. I don't know which is better, really.
Interesting...!!!!!!.
So you're making a 31x32 pixel display ;) x86 gets away with 8 registers -- I'm sure you could write some neat code which uses 8, and displays graphics/text on the other 23
19:40 the only issue i see with the bottom architecture is that you can't use your LED output to debug the state of the other 2 register chips if one of them is faulty, while the top one shows you what's actually on the bus. so any hardware failure or bitflips introduced by e.g. radiation affecting the "source registers" wouldn't show up in the "led register"
Thank you for the clear explanation. I wish you the best of luck. This project is very exciting.
I have a few questions. What's is the effect of the three chip solution on bus loading? Did you consider using 32bit registers?
Very good question! I should have addressed that in the video. Each data line connects to 31 x 3 chips, so 93 (figure 100) inputs. The data input current is a maximum of 5uA, so figure 0.5mA. Most of the chips I'm using can drive much more than that, so I should be very safe.
As for the 32bit registers, I looked and couldn't find any.
32bit register parts would probably be BGA packages. At 32bits I'd just stick to doing things in an FPGA.
Subbed...neat :)
I don't know why but you remind me of Thomas Anderson so much.
Just a thought - did you ever consider color coding the debug LEDs (ie making the source select bits green) so that they're easier to distinguish? I know they're spaced out from the rest of the bits, but it was a little confusing from far away. It looks like you're pretty early on in the project, so I thought I would suggest it. Either way, very nice video! I can't wait to see future videos as this project develops!
It seems like it would be a good idea. I'm just a bit nostalgic about red LEDs. Also, eventually there would be an acrylic cover with labels. I'll have to think about it!
Great project. Are you publishing schematics/design docs?
ZoopDragon GitHub links in the description.
At 36:15 I thought, maybe I should comment with a joke about left/right confusion... Then you said the joke I had in mind. Perfect haha
Good. Unfortunately around 8: 30 focus starts warbling and I can't watch it. Sorry.
Actually cleaned up pretty good pretty quick. Fun video thanks.
Real life Sheldon Cooper talking about RISC!!! Good vid, thanks!!! Big hug from Argentina
RISC-V seems very MIPS inspired...
RISC-V was designed by Dave Patterson of Berkeley, who coined the term RISC back in the early 1980s. He and colleague John Hennesey of Stanford literally wrote the book on processor architecture. In the early '80s, Hennesey took a sabatical from Stanford to start MIPS. So, you could say MIPS is an uncle of RISC-V.
www.amazon.com/Computer-Architecture-Sixth-Quantitative-Approach/dp/0128119055/ref=pd_sim_14_3?_encoding=UTF8&pd_rd_i=0128119055&pd_rd_r=ZR0GG3SRQKKDGMFZXPE2&pd_rd_w=H9zdE&pd_rd_wg=Ribd6&psc=1&refRID=ZR0GG3SRQKKDGMFZXPE2
It's a purebred RISC, like MIPS, but there are as many differences as similarities. A lot of MIPS instructions are missing, generally for good reason, and there are a few new instructions even in the base ISA, like proper branch conditions to make up for the lack of status reg. The encoding is similar in ways that are useful (keeping register specifiers in the same location) and different in ways that are genius (the way that immediates are encoded for example). This is all just looking at the base integer ISA -- if you look at the extensions, and the way the instruction set is designed to be extended, there is a whole lot of other stuff going on. Not to mention that it's one of the densest instruction sets around, once you add the C (compressed instructions) extension, and AFAIK is *the* densest 64-bit ISA bar none.
Luke Wren Could you elaborate what's genius about the immediate encoding? I'ld be interested in it.
The immediate bits are "scrambled" in the instructions in a way that seems bizarre, but actually shortens critical path and reduces gate count.
One feature is that the sign bit of the immediate (and *all* immediates are sign-extended, even for logicals... actually really useful, e.g. XORI x, -1 gives you NOT x) is *always* in the same location for 32 bit instructions, and has a constant location in the 16-bit extension too. Sign extension is often critical path on decode, partly due to the huge fanout of the sign bit, and having it in a consistent place removes muxes from your critical path.
They also scramble bits around to ensure that, when possible, a given bit in the immediate comes from a fixed position in the instruction word. For example, the immediate for a branch instruction is left shifted by 1 to increase branch range, but rather than just use the S (store) format and require a left shift of the immediate during decode, they move things around so that:
- sign bit (immediate bit 11 for S format, immediate bit 12 for B format) stays in the same place in the instruction word
- immediate bits 10...1 are in the same positions in the instruction
- immediate bit 11 in the B format is in the same place as immediate bit 0 in the S format
And the overall gate count of immediate decoding is greatly reduced with this kind of strategy. There are 6 instruction formats for 32-bit instructions, 2 of which are just shift specialisations of other formats (for example, B is a specialisation of S above). It gets a little more crazy for the 16-bit formats, but the strategy is the same.
If you want the full details, then check out these pages in the v2.2 spec (most recent one):
Page 12 - base 32bit formats (R I S B U J)
Page 70 - 16bit format listing (although without full information on immediate decode)
Page 82 - 16bit instruction listing, with more detailed information on immeditates
teach me master!
This will be cool to see. Why didn't you go with right-angle SMT LEDs?
Rick too expensive!
Ah, gotcha.
You have left-right confusion too? I thought that was just me!
Is there a board thickness requirement for the cards that go into the PCIe slot? Is the usual thickness good enough or should you bump up the thickness for card slots
"Standard" 1.6mm thickness.
really good content here, hope channels like this got more subs than those child targeted shitty channels
hello sir, I want to ask what the differences are in the design of the Arm chipset with x86 and what does each architecture base mean?
Would it work for an 8 bit operating system where a compression would be 4 8 bit instructions per cycle where Z is 4 X 8 bit instructions to run a 32 bit register?
OR L where where is 4 compresses 32 bit instructions compressed to 8 bits? These would be custom instructions for speeding up instructions that are used most often.
Why not SMD LEDs?
12:30 Might want to try to avoid situations where you explain that the output goes to the source. :/ I guess it's referring to mosfets source and drain and how the flow of electrons is from negative to positive. Or how my electronics teacher put it: We had a 50% chance to guess polarity right and well... tough luck. ;)
5:08 1965 called. DEC wants it's flip chips back... :)
Are you continuing this project?
DarklinkXXXX Yes, but I had to do some yak-shaving first. See my videos on transmission lines.
@@RobertBaruch why did you abandon FPGA project?
You draw your zeros like this Ø and I've had TAs in computer science do the same thing, so I have to ask; is there a specific reason you do this related to the field, or is it just a coincidence?
It's related to the field, and differentiates the letter O from the numeral 0.
FPGA for me. Thanks!
Cannot see this mentioned elsewhere in the comments... You mention the LEDs will be consuming a couple of milliamps (since you state 3.3V and 1500 ohms)... However, you've neglected to include the LED forward voltage (which is around 2.1V for a red LED). Therefore, there is only about 0.8mA flowing through the resistors / LEDs ((3.3 - 2.1) / 1500). This should still be plenty of juice for _most_ LEDs to actually glow without requiring a nuclear power plant to supply them!.
Vector instructions as in graphics or?.
SIMD
Have you thought about Patreon?
www.patreon.com/user?u=3190442
The "A" is for Atomic? Like for Quantum computing?
No, like CAS.
It means instructions that can't be interrupted part way through. A micro can receive a signal that says "stop everything and pay attention to me". Add works this way. "Atomic" instructions are un-cuttable. Once that instruction starts it is guaranteed to finish and ignore all signals.
These types of instructions are important when multitasking and allow competing processes to take turns using shared memory.
Tell me more about "Completely license free" (0:55)
Nice 32bit risc though it takes bigger balls to do it without ICS but that's not the goal. Risc is all about simplicity
x0 register is always zero. Creators of risc-v was able to go futher and make x1 always 1, the 1 is friquent encountered constant too.
You claim you aren't using an FPGA to create it, but instead using Discrete Logic. I remember writing my own CPUs in discrete logic (not RISC-V, just a small custom CPU) that the software I was using (Xilinx ISE) then took and provided I added mappings to inputs and outputs, flashed it onto the FPGA. I used structural modeling the first time around, and behavioral (VHDL) the second time I designed the more complex 2.0 version of it. Confirming it works, I could of just taken my schematic straight to an hardware manufacturer to create a ASIC/dedicated circuit.
I guess my question/comment is, when you say you aren't using an FPGA, do you mean you don't care to migrate your design to an FPGA or - and I'm thinking this may be the case - is it that today's FPGA's and their respective libraries/programs consist of board specific libraries/components that make it quicker to create something, therefore abstracting all the discrete logic hence your reasoning.
Thanks