Modulo Counter Using Asynchronous Counter: Basics, Circuit, Designing, Working, and Waveforms

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  • Опубликовано: 11 янв 2025

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  • @EngineeringFunda
    @EngineeringFunda  Год назад +2

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  • @ektachhaila6958
    @ektachhaila6958 3 года назад +8

    The explanation is just amazing. It is maintaining my curiosity that's the best part.
    Thankyou Professor :)

    • @EngineeringFunda
      @EngineeringFunda  3 года назад +3

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  • @CNILOYBARUA
    @CNILOYBARUA Год назад +1

    Great video sir ,LOVE from Bangladesh

    • @EngineeringFunda
      @EngineeringFunda  Год назад

      Your Appreciations, care and share matters a lot to me. #EnginneringLove.
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  • @udaychauhan395
    @udaychauhan395 2 года назад +5

    Thank you sir, lots of love from IIT Guwahati 👏🥰

    • @EngineeringFunda
      @EngineeringFunda  2 года назад +1

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  • @nirmalchoudhary3196
    @nirmalchoudhary3196 2 года назад +4

    Nice teaching skill 😄

    • @EngineeringFunda
      @EngineeringFunda  2 года назад

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  • @shamimhasan8302
    @shamimhasan8302 Год назад +1

    Thank you Sir from Bangladesh.

    • @EngineeringFunda
      @EngineeringFunda  Год назад +2

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  • @Thammudu_____
    @Thammudu_____ 3 года назад +5

    1:05 there is no moment in hand so I thought my video got stuck but actually what happened 😂

  • @deadpool4098
    @deadpool4098 Год назад +2

    At 8:16 - 8:17 I think there should be AND gate instead of NAND gate because In the video of preset and clear you taught that clear works when clear = 0. Since it is already active low, a high signal should be applied to clear. Otherwise what is point of using two continuous NOT gates (1 inside NAND and 1 in active low bubble) before applying signal to flipflop cell.

    • @EngineeringFunda
      @EngineeringFunda  Год назад

      Bubble means active low

    • @srujana9756
      @srujana9756 Год назад

      I think for active low clear (if clear=0 then output will be zero) so if we give nand gate it makes all output to '1'..so I think AND gate is correct for this circuit

  • @mahadevc9880
    @mahadevc9880 2 года назад +1

    Best explanation

    • @EngineeringFunda
      @EngineeringFunda  2 года назад

      Your positive comments motivates me.
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      Love from you guys means a lot to me.
      My goal is to create largest community of engineers in entire globe. Please help me by sharing this playlist with your friends.

  • @gamar1226
    @gamar1226 4 года назад +4

    Thank you professor

    • @EngineeringFunda
      @EngineeringFunda  4 года назад +2

      Love and happiness of students is my ultimate goal, God bless you 🙏, keep learning and keep progressing.

  • @comforttutorials4286
    @comforttutorials4286 3 года назад +1

    very helpful....thank you

    • @EngineeringFunda
      @EngineeringFunda  3 года назад

      Your positive comments motivates me.
      Teachers like me just wants positive comment from student.
      Love from you guys means a lot to me.
      My goal is to create largest community of engineers in entire globe. Please help me by sharing this playlist with your friends.

  • @SaiKiran38252
    @SaiKiran38252 4 года назад +1

    Excellent explanation.

    • @EngineeringFunda
      @EngineeringFunda  4 года назад

      Love and happiness of students is my ultimate goal, God bless you 🙏, keep learning and keep progressing.

  • @mohithkumar4083
    @mohithkumar4083 4 года назад +1

    Well teaching sir

    • @EngineeringFunda
      @EngineeringFunda  4 года назад

      Your positive comments motivates me, Thanks and welcome 🙏

  • @karansaini4384
    @karansaini4384 Год назад +1

    Thankyou sir❤ NIT Jalandhar

    • @EngineeringFunda
      @EngineeringFunda  Год назад

      Your Appreciations, care and share matters a lot to me. #EnginneringLove.
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  • @VAISHNADEVIGECEUG-
    @VAISHNADEVIGECEUG- 3 года назад +1

    THANK YOU SIR

    • @EngineeringFunda
      @EngineeringFunda  3 года назад

      Your positive comments motivates me.
      Teachers like me just wants positive comment from student.
      Love from you guys means a lot to me.
      My goal is to create largest community of engineers in entire globe. Please help me by sharing this playlist with your friends.

  • @ManishSharma-pe7ip
    @ManishSharma-pe7ip 9 месяцев назад

    0:33 0:37 0:37 0:39 0:39 0:43 0:43 0:43

  • @muntasirmoon9188
    @muntasirmoon9188 Год назад +1

    thanks ,understood

    • @EngineeringFunda
      @EngineeringFunda  Год назад +1

      All the subjects playlist of Engineering Funda is available in comment section. Share it with your friends to support us.
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  • @ManishSharma-pe7ip
    @ManishSharma-pe7ip 9 месяцев назад

    0:05 0:11 0:13

  • @chinni949
    @chinni949 9 месяцев назад +1

    sir please make problems on digital electronics for gate

    • @EngineeringFunda
      @EngineeringFunda  9 месяцев назад

      See the playlist, you can,solve any questions on GATE as well.

  • @ashishkumarsharma1323
    @ashishkumarsharma1323 4 года назад +2

    sir i have a doubt! what happens when clear is 1? like in the before cases when the output Q3Q2Q1= 010 or 101? and will it stop after 110? why wont it go till 111?

    • @ganitacademyengineeringeng4153
      @ganitacademyengineeringeng4153 3 года назад +1

      When you use active high clear.. 101 should be given as inputs to And gate

    • @ganitacademyengineeringeng4153
      @ganitacademyengineeringeng4153 3 года назад +1

      After 101,it goes to 000..because all the flipflops are cleared or reset

    • @yashkataria2992
      @yashkataria2992 Год назад +1

      If any one input of nand gate is 0 then the output is 1 so this nand gate will give output as 0 only and only if the input to nand is 110 so when this condition come then nand will give 0 as output and this 0 will goes to clear and reset the counter

  • @logacreationchannel2693
    @logacreationchannel2693 2 года назад

    Thankyou sir .

    • @EngineeringFunda
      @EngineeringFunda  2 года назад

      Your positive comments motivates me.
      Teachers like me just wants positive comment from student.
      Love from you guys means a lot to me.
      My goal is to create largest community of engineers in entire globe. Please help me by sharing this playlist with your friends.

  • @sameerbilla515
    @sameerbilla515 4 года назад

    Sir make video on logic families... please!!!

    • @EngineeringFunda
      @EngineeringFunda  4 года назад

      I will definitely make it but it will take some time.

  • @takefocus2313
    @takefocus2313 2 года назад

    5:05 ..Sir please tell Me..What is LSB and MSB

    • @EngineeringFunda
      @EngineeringFunda  2 года назад +1

      Most Significant Bit is MSB and Least Significant Bit is LSB

  • @vimala8508
    @vimala8508 2 года назад

    For modulo 6 counter we should not take 1 1 0 state.we should stop at 1 0 1 and take clear accordingly???

    • @EngineeringFunda
      @EngineeringFunda  2 года назад

      It will not take 110, it will clear FF at 110

    • @vimala8508
      @vimala8508 2 года назад

      @@EngineeringFunda but unless the state is 1 1 0 how will the clear NAND Gate take it.?

    • @yashkataria2992
      @yashkataria2992 Год назад

      @@vimala8508 state will go to 1 1 0 but as he goes to 110 the clear will do his job and make the output 0 0 0 if we make it for 1 0 1 then it will not count 5 instead of 5 it will give 0 0 0 that's why we take 1 1 0

    • @vimala8508
      @vimala8508 Год назад +1

      @@yashkataria2992 thanks

  • @rohitkrishnan8249
    @rohitkrishnan8249 4 года назад

    So if it changes to any other module counter the circuit diagram changes right?

  • @harvey2355
    @harvey2355 4 года назад

    sir is that any reason to use t flip-flop for design asynchronous counter. which other flip-flop can be use for design asynchronous counters.

    • @EngineeringFunda
      @EngineeringFunda  4 года назад +1

      It gives advantage of toggle and counter needs that only

    • @harvey2355
      @harvey2355 4 года назад

      @@EngineeringFunda can I use any counter for asynchronous as well as synchronous

    • @ganitacademyengineeringeng4153
      @ganitacademyengineeringeng4153 3 года назад +1

      We can also use JK flipflop..with J=K=1

    • @ganitacademyengineeringeng4153
      @ganitacademyengineeringeng4153 3 года назад +1

      @@harvey2355 For asynchronous u need to use jk or T fliflop..but for synchronous u can use any

    • @Thammudu_____
      @Thammudu_____ 3 года назад +2

      @@ganitacademyengineeringeng4153 u r giving the reply but not admin great to see such people like you

  • @TusharKumar-iu4nt
    @TusharKumar-iu4nt 3 года назад +1

    Sir so we can make all these counters by the use of any flip flop?? Only thing is that its connections change...

  • @Force_of_nature_007
    @Force_of_nature_007 Год назад

    there is an error here, when 001 input, clr will happen

  • @SMITPATEL-px7um
    @SMITPATEL-px7um 3 года назад

    can you please help me i need to design n-bit sunchronus counter please help me

  • @TehreemMalik-ge2du
    @TehreemMalik-ge2du 8 месяцев назад

    Sir snd me your pen collection I like it 😂

  • @MRGAMING-xc8mw
    @MRGAMING-xc8mw Год назад +1

    Thank u sir

    • @EngineeringFunda
      @EngineeringFunda  Год назад

      All the subjects playlist of Engineering Funda is available in comment section. Share it with your friends to support us.
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