Your presentation is wonderful. The amount of work involved in your compiler… and making it avaliable as open source… definitely helping to enable the next generation of developers. A life time of learning is not enough to learn everything in analog/digital ic design.
Thanks for the kind words. I agree that life is a bit short to grasp everything, which is partly why I feel the need to store some of what I've learned over the years in the hope that others might accelerate their learning.
The CDAC schematic does indeed only contain metal resistors. The capacitors are parasitic capacitors between metal lines, so they only appear once the parasitic netlist is extracted. The metal resistors are used to separate nets and get the LVS correct.
1) Yes, quite a few dummies 2) I have not tried EM on the SAR. If you can find EM setup for sky130nm I would try CAP32C_CV, anything more complex might be too much for EM
*ELI5 Abstract* *Project: Making a Special Computer Chip* * *What it is:* I'm working on a tiny computer chip called an ADC. It's like a translator, turning sounds and things we measure into signals the computer understands. * *Tiny Tape-out:* This project lets people like me try to put our designs onto real chips! It's usually very expensive to do this. * *My Design:* I've been working on this for a long time, and it works really well! *Building the Chip with Code* * *Like Lego, but with Code:* I write special code instead of using my hands to build the design. This code is like instructions for building with tiny Lego blocks. * *Changing Sizes:* My code is smart! I can change a few things and make the design bigger or smaller to fit different chips. * *Special Tools:* I need special computer programs to turn my code into the real chip design. It's like having machines that understand my Lego instructions and build the thing. *Testing If It Works* * *Pretend Play:* I use a computer program to pretend my chip is real. I can see how it would work! * *Trying Different Things:* It's like playing with toys on hot days, cold days, and with slow toys or fast toys. My pretend chip needs to work in all those situations. * *Checking for Mistakes:* If I make a change, I check to see if I broke anything in the design, just like making sure my Lego tower doesn't fall! *Getting My Chip Ready* * *Special Drawing:* I need to make a special drawing of my chip that the chip factory can understand. * *Almost Done:* My design is working well, but I need to fix a few small things before sending in my drawing. *I'm excited to share my chip design with everyone!* *Abstract* This video transcript describes the development of a compiled analog-to-digital converter (ADC) design and the process of porting it to the Skywater 130nm process for submission to the TinyTapeout initiative. It is based on work of the guy that made the ADC that is in the Hubble Space Telescope. *Key Points:* * *Compiler-Based Design:* The ADC design is unique in that it is compiled, meaning the layout is generated from code that captures design knowledge and rules. This approach offers flexibility and portability. * *Performance and Portability:* The compiler system began as a way to create high-performance ADCs. It has been successfully ported between multiple technologies (including 28nm, 22nm, and Skywater 130nm), demonstrating its adaptability. * *System Overview:* The compilation process involves defining the circuit in Spice netlists, describing placement, and encoding routing instructions. A Python transpiler converts this intermediate format (cic) into layout (Magic), schematics, and simulation files. * *Challenges and Advantages:* The system's strength lies in porting to different technologies once the architecture is encoded. However, the initial setup and encoding of designs can be complex. * *Verification and Tape-out:* The speaker outlines a verification plan for the SAR ADC and describes the simulation setup. They conclude by discussing the process of generating the GDS file for the TinyTapeout submission.
*Summary* *Project: Designing an Analog-to-Digital Converter (ADC) for Chip Submission* * *0:00* Introduction to the project: submitting an open-source ADC design for a tape-out (the process of fabricating a chip). The speaker highlights the affordability made possible by the TinyTapeout initiative. * *1:56* The speaker's ADC design is the result of years of work, inspired by a 2009 conference and collaboration. * *4:08* Explanation of the system they've developed to generate chip layouts programmatically, focusing on creating high-performance ADCs. *The ADC Design* * *7:21* Overview of the ADC, which uses a common SAR design with specialized techniques for efficiency and portability across different chip fabrication processes. * *14:16* Key aspect: the ADC was compiled, meaning its layout was generated from code, a unique approach in this field. *Compiling ADCs* * *14:49* The speaker boasts that their compiled ADC achieves performance comparable to the best ADCs. * *15:08* Explanation of the compilation process: layout is generated from code that captures design knowledge. The initial system used Perl, but it was ported to C++ for speed and with the goal of making it open-source. * *16:50* Key components of the compilation system: netlists (describing connectivity), placement information, and an object description file. * *18:32* The speaker's motivation to port their system to Skywater 130, an open-source process, to enable sharing their work. *How the Design is Encoded* * *18:43* The goal is to put everything needed for layout generation into text files. The system is intentionally simple, without AI. * *19:17* The design process starts with basic rules, defining even the transistor level. * *22:06* Example using a Spice netlist to describe connectivity in an inverter. The compiler uses this information for device placement. * *25:22* Moving to complex cell design, using Spice netlists for placement and JSON for routing instructions. *The Power of Compilation* * *29:33* Demonstration of how the system makes porting to different technologies easy. * *30:58* Starting the process of porting the ADC design to the Skywater 130 process. * *33:22* Challenges: the system is difficult to use, requiring both analog design and coding skills, which are rarely found together. *How the System Works* * *34:34* Overview of the process: start with an idea in Xschem, generate a Spice netlist, define layout and routing, then use tools to create the layout files. * *37:13* Demonstration of the compilation process and GUI for visualization. *Porting to Skywater 130* * *46:44* The compiler enables porting to technologies like Skywater 130, and the designs pass DRC/LVS checks. * *48:03* Explanation of using the TinyTapeout analog template and setting up the design. * *50:45* Manual routing in Magic was required for some parts of the design. * *51:10* Explaining the CIC file (intermediate format) and its structure. * *53:17* Highlighting the challenge in writing the JSON and Spice files for the system. *Project Setup and Simulation* * *55:44* Overview of project organization, using submodules for reusability and scripts to streamline tasks. * *57:20* The compiled schematic, while functional, is not visually appealing. * *59:13* Routing in Magic, demonstrating its speed and DRC features. * *61:41* Explanation of where DRC/LVS commands are found and how to adapt them. * *1:03:56* Demonstrating the ease of working with older design versions using LVS for verification. * *1:04:26* Explanation of the simulation setup, including parasitic extraction and the importance of simulating across different process corners. *Verification, Analysis, and Tape-out Preparation* * *1:06:28* The speaker's verification plan for the ADC. * *1:07:44* Tools and scripts used to manage simulation complexity. * *1:12:33* Analyzing simulation results using Python scripts. * *1:15:35* Process of generating the GDS file for tape-out, and final fixes. *Conclusion* * *1:16:53* Gratitude for the TinyTapeout initiative and the feeling of accomplishment in having the design ready. * *1:17:19* Emphasis on the open-source nature of the project and encouragement for others to explore and learn. Disclaimer: I used gemini advanced 1.0 (2024.03.04) to summarize the video transcript. This method may make mistakes in recognizing words and it can't distinguish between speakers.
Fantastic video, I am delighted to see analog getting some much love!
Your presentation is wonderful. The amount of work involved in your compiler… and making it avaliable as open source… definitely helping to enable the next generation of developers. A life time of learning is not enough to learn everything in analog/digital ic design.
Thanks for the kind words. I agree that life is a bit short to grasp everything, which is partly why I feel the need to store some of what I've learned over the years in the hope that others might accelerate their learning.
Congrats and thank you for showing your insights!
i really appreciate these videos
thanks!
Virtuoso
Super interesting! Lots of great info here
Great presentation. How many metal layers can be used in this projetc? Thanks
On tinytapeout I believe it's max up to Metal 4 (locali, metal 1 - 4), but I'd check tinytapeout.com/specs/ to be sure.
Great video as always. I take a look inside the capacitor's DAC and I saw there were resistors inside it. am I missing something?
The CDAC schematic does indeed only contain metal resistors. The capacitors are parasitic capacitors between metal lines, so they only appear once the parasitic netlist is extracted. The metal resistors are used to separate nets and get the LVS correct.
Did you place dummy transistors in the layout ? Active devices might cause leakage without them. Also does it allow to do EM simulations ?
1) Yes, quite a few dummies 2) I have not tried EM on the SAR. If you can find EM setup for sky130nm I would try CAP32C_CV, anything more complex might be too much for EM
amazing!
*ELI5 Abstract*
*Project: Making a Special Computer Chip*
* *What it is:* I'm working on a tiny computer chip called an
ADC. It's like a translator, turning sounds and things we measure
into signals the computer understands.
* *Tiny Tape-out:* This project lets people like me try to put our
designs onto real chips! It's usually very expensive to do this.
* *My Design:* I've been working on this for a long time, and it works
really well!
*Building the Chip with Code*
* *Like Lego, but with Code:* I write special code instead of using my
hands to build the design. This code is like instructions for
building with tiny Lego blocks.
* *Changing Sizes:* My code is smart! I can change a few things and
make the design bigger or smaller to fit different chips.
* *Special Tools:* I need special computer programs to turn my code
into the real chip design. It's like having machines that understand
my Lego instructions and build the thing.
*Testing If It Works*
* *Pretend Play:* I use a computer program to pretend my chip is
real. I can see how it would work!
* *Trying Different Things:* It's like playing with toys on hot days,
cold days, and with slow toys or fast toys. My pretend chip needs to
work in all those situations.
* *Checking for Mistakes:* If I make a change, I check to see if I
broke anything in the design, just like making sure my Lego tower
doesn't fall!
*Getting My Chip Ready*
* *Special Drawing:* I need to make a special drawing of my chip that
the chip factory can understand.
* *Almost Done:* My design is working well, but I need to fix a few
small things before sending in my drawing.
*I'm excited to share my chip design with everyone!*
*Abstract*
This video transcript describes the development of a compiled
analog-to-digital converter (ADC) design and the process of porting it
to the Skywater 130nm process for submission to the TinyTapeout
initiative. It is based on work of the guy that made the ADC that is in the
Hubble Space Telescope.
*Key Points:*
* *Compiler-Based Design:* The ADC design is unique in that it is
compiled, meaning the layout is generated from code that captures
design knowledge and rules. This approach offers flexibility and
portability.
* *Performance and Portability:* The compiler system began as a way to
create high-performance ADCs. It has been successfully ported
between multiple technologies (including 28nm, 22nm, and Skywater
130nm), demonstrating its adaptability.
* *System Overview:* The compilation process involves defining the
circuit in Spice netlists, describing placement, and encoding
routing instructions. A Python transpiler converts this intermediate
format (cic) into layout (Magic), schematics, and simulation files.
* *Challenges and Advantages:* The system's strength lies in porting
to different technologies once the architecture is encoded. However,
the initial setup and encoding of designs can be complex.
* *Verification and Tape-out:* The speaker outlines a verification
plan for the SAR ADC and describes the simulation setup. They
conclude by discussing the process of generating the GDS file for
the TinyTapeout submission.
*Summary*
*Project: Designing an Analog-to-Digital Converter (ADC) for Chip Submission*
* *0:00* Introduction to the project: submitting an open-source ADC
design for a tape-out (the process of fabricating a chip). The
speaker highlights the affordability made possible by the
TinyTapeout initiative.
* *1:56* The speaker's ADC design is the result of years of work,
inspired by a 2009 conference and collaboration.
* *4:08* Explanation of the system they've developed to generate chip
layouts programmatically, focusing on creating high-performance
ADCs.
*The ADC Design*
* *7:21* Overview of the ADC, which uses a common SAR design with
specialized techniques for efficiency and portability across
different chip fabrication processes.
* *14:16* Key aspect: the ADC was compiled, meaning its layout was
generated from code, a unique approach in this field.
*Compiling ADCs*
* *14:49* The speaker boasts that their compiled ADC achieves
performance comparable to the best ADCs.
* *15:08* Explanation of the compilation process: layout is generated
from code that captures design knowledge. The initial system used
Perl, but it was ported to C++ for speed and with the goal of making
it open-source.
* *16:50* Key components of the compilation system: netlists
(describing connectivity), placement information, and an object
description file.
* *18:32* The speaker's motivation to port their system to Skywater
130, an open-source process, to enable sharing their work.
*How the Design is Encoded*
* *18:43* The goal is to put everything needed for layout generation
into text files. The system is intentionally simple, without AI.
* *19:17* The design process starts with basic rules, defining even
the transistor level.
* *22:06* Example using a Spice netlist to describe connectivity in an
inverter. The compiler uses this information for device placement.
* *25:22* Moving to complex cell design, using Spice netlists for
placement and JSON for routing instructions.
*The Power of Compilation*
* *29:33* Demonstration of how the system makes porting to different
technologies easy.
* *30:58* Starting the process of porting the ADC design to the
Skywater 130 process.
* *33:22* Challenges: the system is difficult to use, requiring both
analog design and coding skills, which are rarely found together.
*How the System Works*
* *34:34* Overview of the process: start with an idea in Xschem,
generate a Spice netlist, define layout and routing, then use tools
to create the layout files.
* *37:13* Demonstration of the compilation process and GUI for
visualization.
*Porting to Skywater 130*
* *46:44* The compiler enables porting to technologies like Skywater
130, and the designs pass DRC/LVS checks.
* *48:03* Explanation of using the TinyTapeout analog template and
setting up the design.
* *50:45* Manual routing in Magic was required for some parts of the
design.
* *51:10* Explaining the CIC file (intermediate format) and its
structure.
* *53:17* Highlighting the challenge in writing the JSON and Spice
files for the system.
*Project Setup and Simulation*
* *55:44* Overview of project organization, using submodules for
reusability and scripts to streamline tasks.
* *57:20* The compiled schematic, while functional, is not visually
appealing.
* *59:13* Routing in Magic, demonstrating its speed and DRC features.
* *61:41* Explanation of where DRC/LVS commands are found and how to
adapt them.
* *1:03:56* Demonstrating the ease of working with older design
versions using LVS for verification.
* *1:04:26* Explanation of the simulation setup, including parasitic
extraction and the importance of simulating across different process
corners.
*Verification, Analysis, and Tape-out Preparation*
* *1:06:28* The speaker's verification plan for the ADC.
* *1:07:44* Tools and scripts used to manage simulation complexity.
* *1:12:33* Analyzing simulation results using Python scripts.
* *1:15:35* Process of generating the GDS file for tape-out, and final
fixes.
*Conclusion*
* *1:16:53* Gratitude for the TinyTapeout initiative and the feeling
of accomplishment in having the design ready.
* *1:17:19* Emphasis on the open-source nature of the project and
encouragement for others to explore and learn.
Disclaimer: I used gemini advanced 1.0 (2024.03.04) to summarize the
video transcript. This method may make mistakes in recognizing words
and it can't distinguish between speakers.
Sir can you please make some tutorials on simulation in xschem from scratch.
As there is no proper tutorials on open source tools in YT.
The closest I have is probably ruclips.net/video/go02Z-_3x3s/видео.htmlsi=pnmMrV3nhDvUapqo
Most designers are not coders , pretty divergent discipline