As far as I know one clock cycle is not mean one clock impulse. So the statement at 5:00 is wrong. You cannot access the contents in 0.5 ns at 2Ghz! That would mean that one clock cycle is one clock impulse which is almost impossible since you have to have to fetch the instruction to access the contents first which at least is one clock impulse leaving. So if it were a impossible perfect optimized system it could maybe access it in 2 clock impulses which is 1 ns!
This talk is amazing! 👍
This was a really good presentation!
Thanks
As far as I know one clock cycle is not mean one clock impulse. So the statement at 5:00 is wrong. You cannot access the contents in 0.5 ns at 2Ghz! That would mean that one clock cycle is one clock impulse which is almost impossible since you have to have to fetch the instruction to access the contents first which at least is one clock impulse leaving. So if it were a impossible perfect optimized system it could maybe access it in 2 clock impulses which is 1 ns!
Will you speak with me and explain family sockets
Mike acton