FPGA PROTOTYPING TIPS & HACKS Part 3 | RESET | Power On Reset

FPGA PROTOTYPING EXPERIENCE TIPS & HACKS Part 3
FPGA PROTOTYPING EXPERIENCE TIPS & HACKS Playlist:-
• FPGA PROTOTYPING EXPER...
#TechnicalBytes#FPGA#FPGATips&Hacks#VLSI#RESET #PowerOnReset

[@meenugarg1102]

Thanks sir for quick tips 🙏

[@TechnicalBytes]

Always welcome

[@sivasaijaswanthyadala428]

Hi Sir, If I consider a reg [1:0] val assigned an INIT of 2 and in the asynchronous reset I assigned it as 3 what would be the initial value the global set reset considers.

[@SushilKumar-dv6wt]

POWER ON RESET only works for asynchronous reset or for both synchronous and asynchronous reset?????

[@10lbslighter]

Asynchronous reset example is WRONG. Sensitivity list should be always @(posedge clk , rst)