I built the clock circuit exactly like yours but there is still some occasional bouncing on the clock signal, which skips some steps, observable with scope too. Do you know what could be the cause?
I'm sorry to hear that! The first thing that comes to mind is the resistor/capacitor value that determines the debouncing circuit's time delay. The button you use might have more bounce than the one I had on the breadboard (my button might also deteriorate over time, causing me to run into the same problem you're seeing). My guess would be to try and increase the capacitor/resistor size to increase the debouncing dead time, such that slower bounces are still properly suppressed. Let me know if you see any change!
I recently saw your fantastic series and try to build the CPU in a simulator. By implementing the reset sync I noticed a problem with being the first D Input constant high and simultaneously pushing the reset pin high. This should lead to an unknown state at the output since set and reset are both high then. To avoid that I used J-K Flipflops, this works better, but if I keep the reset button pressed the output will toggle then witch each clock tick. What do I miss?
I found it myself, the 74HC175 uses a flipflop with a asynchronous set and clear and a synchronous data input. The set is forced to low and the clear resets the flipflop immediately.
Yes, that's it! 🙂 The async reset on D flip-flops usually overrides any clock or data inputs, and will force the output low. Once the reset is released, the clock should cause the constant high input to be stored and propagate through the chain of registers. It's interesting that you ran into this issue in a simulator. Do you know what kind of register that simulator uses? This should be the normal D-type flip-flop behavior. But if the simulator uses some form of JK or SR flip-flop as you describe, you might get that weird behavior.
Thank you for this great content. Learned a lot.
Awesome - Loving the detail and shared knowledge, excellent 👍
Great job dude, keep going!!!!
I built the clock circuit exactly like yours but there is still some occasional bouncing on the clock signal, which skips some steps, observable with scope too. Do you know what could be the cause?
I'm sorry to hear that! The first thing that comes to mind is the resistor/capacitor value that determines the debouncing circuit's time delay. The button you use might have more bounce than the one I had on the breadboard (my button might also deteriorate over time, causing me to run into the same problem you're seeing). My guess would be to try and increase the capacitor/resistor size to increase the debouncing dead time, such that slower bounces are still properly suppressed. Let me know if you see any change!
@@fabianschuiki I replaced the 470nF with a 1uF, and it seems to do the trick, thanks!
Great, glad to hear! 🎉🥳
I recently saw your fantastic series and try to build the CPU in a simulator. By implementing the reset sync I noticed a problem with being the first D Input constant high and simultaneously pushing the reset pin high. This should lead to an unknown state at the output since set and reset are both high then. To avoid that I used J-K Flipflops, this works better, but if I keep the reset button pressed the output will toggle then witch each clock tick.
What do I miss?
I found it myself, the 74HC175 uses a flipflop with a asynchronous set and clear and a synchronous data input. The set is forced to low and the clear resets the flipflop immediately.
Yes, that's it! 🙂 The async reset on D flip-flops usually overrides any clock or data inputs, and will force the output low. Once the reset is released, the clock should cause the constant high input to be stored and propagate through the chain of registers.
It's interesting that you ran into this issue in a simulator. Do you know what kind of register that simulator uses? This should be the normal D-type flip-flop behavior. But if the simulator uses some form of JK or SR flip-flop as you describe, you might get that weird behavior.
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