in your previous year lecture on DRAM, the idea of splitting a DRAM bank into near/far (fast/slow) halves was mentioned. What can be done to get lower latency memory in existing systems? Would it be possible to set the SPD on a DIMM with false row information? Example: saying the DRAM chips have 1 fewer row address bit than it actually has? I am assuming the high row address bit represents the half of the bank that is furthest away from the sense amp, allowing lower latency? A 50% or even 75% reduction in capacity is not an issue
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in your previous year lecture on DRAM, the idea of splitting a DRAM bank into near/far (fast/slow) halves was mentioned. What can be done to get lower latency memory in existing systems? Would it be possible to set the SPD on a DIMM with false row information? Example: saying the DRAM chips have 1 fewer row address bit than it actually has? I am assuming the high row address bit represents the half of the bank that is furthest away from the sense amp, allowing lower latency? A 50% or even 75% reduction in capacity is not an issue
Thanks for nice lecture
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