I designed pro broadcast video equipment for decades - NTSC, PAL, up to 4K. This counter plus decode logic plus a register to retime the signals is exactly my preferred implementation. Meat and potatoes of video design. Sometimes folding the decode logic into a PROM addressed by the counter for easy of modification, althouh with FPGAs/CPLDs that's not such a big deal. Nice starting point.
Thanks. I can't take credit as I took the idea from someone else's design, but it's good to know that this is a tried and tested technique. I really feel that I have learnt something very important and useful here.
Hi, nice video. How do you plan to deny access to CPU during video circuitry time slots? Do you do this by asserting the WAIT line and buffering the BUSses or do you assert a BUS Request condition? thx for your explanation.
The cpu busses and video busses are separate. You might describe that as buffering. I'm hoping I won't need to assert the wait line as the video clock is many times faster than the cpu clock. How ever I will need to check the timing.
Love seeing and understanding the work on timings via the oscilloscope, The text on that seems very small at places on the screen. With eyesight not quite what it was, do these have outputs for a larger external screen to make it easier to read?
No, my one does not seem to have the option of connecting a larger screen. The font size is very small and I have seen other people complaining, but I don't think the font size is adjustable.
The re-timing via the latch causes the signals to appear one stage delayed. I didn't explain that this is already compensated for because the AND gate inputs are all connected to one stage earlier than what we want. So after the 1 stage delay, all the signals are back where we want them.
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I designed pro broadcast video equipment for decades - NTSC, PAL, up to 4K. This counter plus decode logic plus a register to retime the signals is exactly my preferred implementation. Meat and potatoes of video design. Sometimes folding the decode logic into a PROM addressed by the counter for easy of modification, althouh with FPGAs/CPLDs that's not such a big deal. Nice starting point.
Thanks. I can't take credit as I took the idea from someone else's design, but it's good to know that this is a tried and tested technique. I really feel that I have learnt something very important and useful here.
You should add the zilog z0860008psc chip to your computer
Good afternoon. thank you very much for sharing your knowledge
Hi, nice video. How do you plan to deny access to CPU during video circuitry time slots? Do you do this by asserting the WAIT line and buffering the BUSses or do you assert a BUS Request condition? thx for your explanation.
The cpu busses and video busses are separate. You might describe that as buffering. I'm hoping I won't need to assert the wait line as the video clock is many times faster than the cpu clock. How ever I will need to check the timing.
Love seeing and understanding the work on timings via the oscilloscope, The text on that seems very small at places on the screen. With eyesight not quite what it was, do these have outputs for a larger external screen to make it easier to read?
No, my one does not seem to have the option of connecting a larger screen. The font size is very small and I have seen other people complaining, but I don't think the font size is adjustable.
The re-timing via the latch causes the signals to appear one stage delayed. I didn't explain that this is already compensated for because the AND gate inputs are all connected to one stage earlier than what we want. So after the 1 stage delay, all the signals are back where we want them.
spotted a small mistake in my math there
but still well within your timing limit :)
Hey 👋