Dear Prof, I want to thank you for this beautiful explanation of the PLIC by you. I would be grateful, Sir, if you can explain in another video the booting process of a computer. What happens during the booting? I want to know the story of booting. Hope you will make this wish come true.
I have a query regarding the CLAIM process (19:50 of video). 1. Does the PLIC write the ID of the interrupting device in the CLAIM words for each of the enabled targets? 2. Then, when one of the enabled targets is the first to respond, does the PLIC write a 0 in the CLAIM words for the other enabled targets that could not win the interrupt? Else, when the other enabled-targets will read their CLAIM words, they will read the ID of the interrupting device even though the interrupt has already begun to be handled by the winner target?
You mentioned (at around 20:00) that a core may be servicing several interrupts simultaneously. How is that possible. Isn't it the case in RISC-V that when context switch happens and Handler starts execution all external interrupts are disabled for that particular HART through mstatus register?
@@echoptic775 Not many people use RISC-V yet. Some schools use it because it's free. Companies are starting to use it more because the ecosystem is maturing. It's a good choice for computer engineering education.
The MIT course that teaches xv6 has switched to Risc-V and other schools may do the same. I wanted to appeal to those students. I also want to be “modern” and Risc-V seems more modern. Also, there are other videos out there for the x86 version, but I didn’t see any for Risc-V. Also, I know more about the Risc-V architecture than x86. Also, there is not much difference in the xv6 code, so it doesn’t really matter which I computer it runs on. And I agree that Risc-V is the future and x86 is the past.
Best explanation of level sensitive vs edge sensitive interrupts I've ever heard.
Dear Prof, I want to thank you for this beautiful explanation of the PLIC by you. I would be grateful, Sir, if you can explain in another video the booting process of a computer. What happens during the booting? I want to know the story of booting. Hope you will make this wish come true.
I have a query regarding the CLAIM process (19:50 of video).
1. Does the PLIC write the ID of the interrupting device in the CLAIM words for each of the enabled targets?
2. Then, when one of the enabled targets is the first to respond, does the PLIC write a 0 in the CLAIM words for the other enabled targets that could not win the interrupt? Else, when the other enabled-targets will read their CLAIM words, they will read the ID of the interrupting device even though the interrupt has already begun to be handled by the winner target?
You mentioned (at around 20:00) that a core may be servicing several interrupts simultaneously. How is that possible. Isn't it the case in RISC-V that when context switch happens and Handler starts execution all external interrupts are disabled for that particular HART through mstatus register?
Why did u choose the ricv specifically? Why not showcase x86 or arm?
@Felicitas Pojtinger but no one uses riscv?
@Felicitas Pojtinger who is using it tho?
@@echoptic775 Not many people use RISC-V yet. Some schools use it because it's free. Companies are starting to use it more because the ecosystem is maturing. It's a good choice for computer engineering education.
In fact,now the risv-v is encouraged by the MIT official.Because it's fater and don't have many history problem like x86
The MIT course that teaches xv6 has switched to Risc-V and other schools may do the same. I wanted to appeal to those students. I also want to be “modern” and Risc-V seems more modern. Also, there are other videos out there for the x86 version, but I didn’t see any for Risc-V. Also, I know more about the Risc-V architecture than x86. Also, there is not much difference in the xv6 code, so it doesn’t really matter which I computer it runs on. And I agree that Risc-V is the future and x86 is the past.