system verilog Assertion (multiple threading)

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  • Опубликовано: 5 ноя 2024

Комментарии • 8

  • @basanthkp4095
    @basanthkp4095 Год назад +2

    Tq bro

  • @pushpendranayak3235
    @pushpendranayak3235 Год назад

    Bahut aandar video

  • @RohitVerma-qu6eu
    @RohitVerma-qu6eu 3 года назад

    btw superb explanation...

  • @RohitVerma-qu6eu
    @RohitVerma-qu6eu 3 года назад

    btw, lecture was superb.

  • @RohitVerma-qu6eu
    @RohitVerma-qu6eu 3 года назад

    $rose-> if let say "a" changes from 0->1 within clock period than it will get "true" at posedge only.
    $fell -> if let say "a" changes from 1->0 within clock period than it will get "true" at negedge only.
    After simulation it seems like both [=m:n] & [->m:n] are same but when I am changing it to [=m:n] ##1 b & [->m:n] ##1 b so they shown diff.

  • @RohitVerma-qu6eu
    @RohitVerma-qu6eu 3 года назад +1

    In which company u r?