In this situation, both of the 3 input NAND gates will actually be outputting 1, which means that the latch is going to stay set. If J is putting in 0, clock is putting in 1, but Q' is putting in 0, then that gate's output is 1. On the other side, if K is putting in 0, clock is putting in one, and Q is putting in 1, then that gate is also 1. Therefore, the latch stays set.
Hi, I'm a student at Thaddeus Stevens College of Technology in Lancaster,PA and wouldn't be easier to introduce the clock after the SR Latch and introduce it by useing the Edge-triggered D flip-flop
a device that detects the rising / falling edge of a pulse instead of the pulse itself and gives a 1 value on this edge. the edge of a pulse takes far less time, thus allowing synchronistion problems to be avoided in applications
In toggle mode, how long (or short) can the clock pulse be, e.g. can a push-button be used to toggle and held down for any length to time (assume switch de-bounce implemented) or does it need a pulse that is shorter than the propagation delay?
All the explanation was consistent, some one is trying to say that at 11:35 minute, the JK should stay SET, but that is not the case. It should, as Prof. Jim Pytel has said, go to RESET mode. Nice!!
What if you have an active low preset in between the rising edge clock signals? Would that affect Q, or is that only when the active low preset occurs during a rising edge clock signal?
Can someone explain to me how there's no situation where S' and R' are not simultaneously set and reset? Because if the output of J and K are 0, and Q is assumed to be 1, then Q and Q' will both be 1, which is the invalid mode.
Thankyou Jim for sharing this wealth of knowledge for those who cannot attend college or universities, god bless you friend.
I'm going to be faving all of your vids and liking them, I learn so much from them.
With highest respect sir, i have watched some of your other videos too and they're ALL CRYSTAL CLEAR. Thanks for sharing this.
Thank you so much for this sir. I have a not so good teacher and I really needed this. Thank you again.
You are the best!!
Greetings Ben from Belgium.
In this situation, both of the 3 input NAND gates will actually be outputting 1, which means that the latch is going to stay set. If J is putting in 0, clock is putting in 1, but Q' is putting in 0, then that gate's output is 1. On the other side, if K is putting in 0, clock is putting in one, and Q is putting in 1, then that gate is also 1. Therefore, the latch stays set.
JIM YOU ARE MADE OF AWESOME!
Thank you very much, you explain it way better than our teacher !
Hi, I'm a student at Thaddeus Stevens College of Technology in Lancaster,PA and wouldn't be easier to introduce the clock after the SR Latch and introduce it by useing the Edge-triggered D flip-flop
a device that detects the rising / falling edge of a pulse instead of the pulse itself and gives a 1 value on this edge. the edge of a pulse takes far less time, thus allowing synchronistion problems to be avoided in applications
just wanted to say that u helped me pass my electronics course thanks alot :D
Alright, now that i found this awesome Jim, i can skip my lectures :D
In toggle mode, how long (or short) can the clock pulse be, e.g. can a push-button be used to toggle and held down for any length to time (assume switch de-bounce implemented) or does it need a pulse that is shorter than the propagation delay?
I'm leaving univerrsity right away, it's no damn use! I watch you all the time to clear my doubts haha, you're the BEST
All the explanation was consistent, some one is trying to say that at 11:35 minute, the JK should stay SET, but that is not the case. It should, as Prof. Jim Pytel has said, go to RESET mode.
Nice!!
Great video! Thank you very much.
You are awsome!!!
this is excellent-- i do not under asynchorous -- pls explain meaning of asynchoronous
What if you have an active low preset in between the rising edge clock signals? Would that affect Q, or is that only when the active low preset occurs during a rising edge clock signal?
thank's for the video but i need some help...
how can i make the clock?
just a +5V or do i need pulse generator?
Any reason why you started out with an active low SR latch?
what is the textbook you are using ??? like the example 7 is coming from what text?
prof = useless
mono digital logic design text = not so useful
but you made this crystal clear thanks !!
great explanation! Thank you.....
Great lecture, just in time for my tutorial later. :)
Can someone explain to me how there's no situation where S' and R' are not simultaneously set and reset? Because if the output of J and K are 0, and Q is assumed to be 1, then Q and Q' will both be 1, which is the invalid mode.
thanks man...u r gr8
If only I was going fishing and smoking with Johnny Loco instead
thank you! I finally understand this
If I had invented this device it would a K-K Flip Flop--only useful for toggling.
Could explain me how can I build a FF T? I want to divide frequency using that.
Your videos are very helpful
thanks
It's named after Jack Kilby, he didn't invent it actually.
Can I download This video?
I finally got how this shit works, THanks :)
GREAT!! JUST BRILLIANT!!
I clicked at 9:35
Great Tutorial! Please make more :D
thx, it's great
thank you :)
Wrong minute 11:35 when j0 k1 current stat 1 should stay in 1. look at basic sr latch when set 1 r 0 it sets to 1 !!!
WROING!!!! Minute 11:35 J 0 K1 Current State Q 1... should state in in 1. Look at basic SR when S1 R 0 it sets to 1.
where is the characteristics equation and table
where is the excitation table and equation
I owe this man a pint
Great vid thanks!!
great
"preety cool uh " i like the way u say it ,anyway thx for this vid nw i got no prob wif jk flip flop :)
love you man
i want to fire my professor and hire you.. i love you.. haha..
what's the difference between blind and VERY blind?
nothing to me.
I was looking for minecraft :D
pretty cool, huh. LOL xD.
Toogle heh
1 man is VERY blind
...
Nit-picker. I suppose you nave never made a mistake.
I don't understand this stuff; fail
thank's for the video but i need some help...
how can i make the clock?
just a +5V or do i need pulse generator?