My question is regarding construction of NOT gate. In a P type transistor, if you apply 3v to gate the circuit opens, causing no current to flow in the circuit. And if you apply 0v to gate, the circuit closes and the current flows. That sounds like NOT gate operation. Then why can't we build NOT gate simply using a P-type transistor? Why do we need an N-type too? 46:00
This is shortly explained in D.&S. Harris Comp. Arch. To my knowledge, a p-Mos cannot "pull down" well, meaning, when the circuit is closed, and the source is GND, the p-Mos will transmit a low current swing from 0 to V_t, V_t being the threshhold voltage.
In Digital circuits: we need potential HIGH('1') and Potential GND('0'). if you use only one transistor (P-Type) then you won't have a pull-down network to provide potential GND ('0'). So pull UP and pull Down n/w are important.
Give Frank a raise
robi doxxed
The way Frank teaches is inspiring!
Damn this guy deserves a raise
Frank for Professor
Funny and very interactive during the class. Thanks Frank
Frank is doing very well.
Frank is awesome
what a Great lecture, Thanks Frank
Frank for President! Joke aside, fantastic way of teaching.
derste bir gram anlamadığım konuyu 10/10 anladım ağlıcam şimdi frank hocam allah sizden razı olsun
My question is regarding construction of NOT gate.
In a P type transistor, if you apply 3v to gate the circuit opens, causing no current to flow in the circuit.
And if you apply 0v to gate, the circuit closes and the current flows.
That sounds like NOT gate operation. Then why can't we build NOT gate simply using a P-type transistor? Why do we need an N-type too? 46:00
This is shortly explained in D.&S. Harris Comp. Arch. To my knowledge, a p-Mos cannot "pull down" well, meaning, when the circuit is closed, and the source is GND, the p-Mos will transmit a low current swing from 0 to V_t, V_t being the threshhold voltage.
In Digital circuits: we need potential HIGH('1') and Potential GND('0'). if you use only one transistor (P-Type) then you won't have a pull-down network to provide potential GND ('0'). So pull UP and pull Down n/w are important.
Thank you Dr Frank
谢谢Frank
This man just won the heart of a Funny Indian Guy
At 54:36. Why can’t we put two transistors in series to get AND gate? Why we have to build NAND + NOT ?
You can find the answer in the same lecture from Spring 2021: ruclips.net/video/F_sbW20kTY8/видео.html
Arent lecturec in German in ETH?
The link on page 6 is not working, please fix it.
Sir, is all lectures are recorded there
tough crowd but frank is good
thank you
why do europeans clap for professors after class is over. it's kind of unusual so it's a bit amusing to me haha
50:12 xd.