I'm 2.5 years into my career in ASIC development and these stuff were really missing for me. Good that I stumbled onto this playlist. This should be mandatory in the syllabus, at least in the nano-electronics track. This is basic chip design knowledge, hopefully I'll have better understanding in company meetings after this course.
Hi, I guess you don't "necessarily" need a separate timer for this, but it's a common "safet/emergency" type of thing that is usually included in a SoC platform.
Why won't we have a flash or some kind of secondary storage in this architecture? as any program will be loaded into that memory at first. Can you clear my concepts please :)
So, this is true. There will usually be some sort of ROM that contains the program that runs on the system (firmware). This ROM could be a hard-wired ROM in a really low cost system, an embedded non-volatile memory (usually eFlash), if the process allows this and the program is sufficiently small, or an external Flash chip, connected through an interface, such as SPI. The external flash will increase the system cost, since it will require integrating at least one more chip with the system, but this is something that may be cheaper than an embedded NVM and is often going to be the case. In any case, this list that I overviewed was in no way supposed to be exhaustive, and you will see during the rest of the course that I will overview such external Flash connections. However, when looking at the chip itself, the external Flash connection is covered by the bullet called "peripherals and I/O". Hope that clarified this point.
I'm 2.5 years into my career in ASIC development and these stuff were really missing for me. Good that I stumbled onto this playlist. This should be mandatory in the syllabus, at least in the nano-electronics track. This is basic chip design knowledge, hopefully I'll have better understanding in company meetings after this course.
Thank you Slava
(and I couldn't agree more!)
what a solid video!
Thanks!
Check out the entire course and the rest of my lectures at enicslabs.com/education/
Why do we have a separate watchdog timer? We can also you the standard timers as a watchdog timer.
Hi,
I guess you don't "necessarily" need a separate timer for this, but it's a common "safet/emergency" type of thing that is usually included in a SoC platform.
Why won't we have a flash or some kind of secondary storage in this architecture? as any program will be loaded into that memory at first.
Can you clear my concepts please :)
So, this is true. There will usually be some sort of ROM that contains the program that runs on the system (firmware). This ROM could be a hard-wired ROM in a really low cost system, an embedded non-volatile memory (usually eFlash), if the process allows this and the program is sufficiently small, or an external Flash chip, connected through an interface, such as SPI. The external flash will increase the system cost, since it will require integrating at least one more chip with the system, but this is something that may be cheaper than an embedded NVM and is often going to be the case.
In any case, this list that I overviewed was in no way supposed to be exhaustive, and you will see during the rest of the course that I will overview such external Flash connections. However, when looking at the chip itself, the external Flash connection is covered by the bullet called "peripherals and I/O".
Hope that clarified this point.