An Overview of Security Annotation for Electronic Design Integration (SA-EDI) Standard

Workshop presented at DVCon U.S. 2022
Presented by IPSA WG
By: Sohrab Aftabjahani, member of the IP Security Assurance Working Group
The importance of security in the electronic systems many of us rely on has become obvious to semiconductor design and manufacturing companies but most hardware security assurance practices in industry are still performed manually using proprietary methods. This approach is very expensive, time consuming, and error prone due to the ever- increasing complexity of systems. To address the issue, the Accellera IP Security Assurance (IPSA) Working Group was formed in 2018 by a team of security and EDA experts to work on developing a general and portable IP security specification standard to describe the IP security concerns (threat model) and to guide EDA vendors on how to produce security assurance collateral and use it for the automation of security verification. The specification was approved as an Accellera standard for Security Annotation for Electronic Design Integration (SA-EDI) in 2021. We will give an overview of this standard by going over the related collateral, methodology, a case study of the application of the standard and the roadmap of the standard.
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