We are planning to make a detailed video on this topic. Till we post a video, you can refer to these documents: www.xilinx.com/support/documentation/sw_manuals/xilinx2018_3/ug902-vivado-high-level-synthesis.pdf www.xilinx.com/html_docs/xilinx2019_1/sdaccel_doc/hls-pragmas-okr1504034364623.html
I haven't tried it by myself yet. But these links can help. zipcpu.com/dsp/2017/07/11/simplest-sinewave-generator.html www.element14.com/community/groups/fpga-group/blog/2019/09/20/fpga-waves-2-simple-sinewave www.mathworks.com/matlabcentral/answers/439300-how-to-generate-sine-wave-for-fpga
@@AbhyaasTrainingInstitute Thank you mam I will try.... Keep making FPGA evaluation board verilog code on vivado very few RUclips channel in this fields
Tomorrow I have project review. U made my work so easier mama.. Thanks lot
Great explanation, Please keep continue...
Great job! Thank you. Instead of thanking the instructor, some guy wants to know her hometown? Why?
Can you please share the PPT??
What is fpga technology? Please make videos or any explanation Please
Please make the very long video
Please make some video on Verilog/VHDL
Thanks for your comment! Link to our VHDL video: ruclips.net/video/c6b1W7wu6po/видео.html
mam can u explain why pragma should be in that particular loop and can u say why we need array partition here
We are planning to make a detailed video on this topic. Till we post a video, you can refer to these documents:
www.xilinx.com/support/documentation/sw_manuals/xilinx2018_3/ug902-vivado-high-level-synthesis.pdf
www.xilinx.com/html_docs/xilinx2019_1/sdaccel_doc/hls-pragmas-okr1504034364623.html
Ma'am aap Bihar se hain kya
Verilog
Can we generate sinewave by using FPGA
I haven't tried it by myself yet. But these links can help.
zipcpu.com/dsp/2017/07/11/simplest-sinewave-generator.html
www.element14.com/community/groups/fpga-group/blog/2019/09/20/fpga-waves-2-simple-sinewave
www.mathworks.com/matlabcentral/answers/439300-how-to-generate-sine-wave-for-fpga
@@AbhyaasTrainingInstitute
Thank you mam I will try.... Keep making FPGA evaluation board verilog code on vivado very few RUclips channel in this fields
Some of words are not clear while u talk
So it's a advice to u that while u speak also write main words
Thanks for your advice, Micky! Your point has been noted!!