Gowin FPGA synthesizer array bug? Or a beginner Verilog mistake?

Attempting to troubleshoot a problem with Gowin FPGA Designer Version 1.9.8.05 build(57076) and Sipeed Tang Nano 4K when developing a first HDMI "Hello, world!" demo.
See github.com/juj... for the problematic part.

[@TymexComputing]

Hi - thank you for this Video - 1:30 for me it looks like Hello{ce - turkish iso?}World{e}!!!{spanic inverted !} - maybe just its some 1 default value like in NAND flash? Maybe just character maps is different or its 127+Ascii inverted?
The other thread i would look for is the MCU m3+ that they are advertising :)

[@TymexComputing]

10:00 - oh ok - +1 found :) - i am not much into Verilog or FPGA but this is the second video i found about that GWin chip - the first one was from 2020 and was presenting the EU (British?) Sales team on some exposition - i would ask them for help directly , some examples, manuals - if everything else fails read the manual / ask the manufacturer :)
I have read the code thoroughly and for me it looks like the posedge_hdmi messess with something - pos is the raising edge? Found a text like this - maybe there could be some delay. +1 -1 NOP NOP make some delay - maybe try with some other "dummy NOP" instruction instead?
"You have a race condition between the falling edge of decode and the rising edge of clock.
Zoom in your wave viewer and you’ll probably see composite going high very briefly at that edge.
To fix it, make sure that decode goes low some nonzero time before clock goes high. Or, even better, instead of using a gated clock (google this term if you don’t know it), use decode as an enable signal, and clock as a clock." - some Verilog practitioner's text :) - copy from 2020.08.14th