12 Inverter Rise & Fall Time | Pre Layout Simulation | Virtuoso Cadence | Simulation | gpdk180.

In this video we'll learn about Inverter rise time and fall time to calculate average delay of the cmos inverter in prelayout simulation.
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[@sadi9945]

Brother, I have a question about any circuit's output. When two input signal switches simultaneously then some spikes are generated at output signal. How can I remove those spikes?May I use buffer or something else for delaying two or more input signals? Please make a video on it?

[@vlsiforrookies]

Sure bro, will try to upload. Thank you for the suggestions and keep supporting.

[@kaverihatti686]

Sir can u show how Monte Carlo simulation steps

[@chaudharysachinkumar5662]

Can we use this same approach for finding the correct width for transistors in 6T SRAM? Actually I am facing issues in scaling..

[@vlsiforrookies]

Idk for what purpose you have to scale, if you have to scale for equal rise time and fall time, then you can use this approach otherwise not. Hope this helps

[@chaudharysachinkumar5662]

@@vlsiforrookies can you share your linkedin profile so that i can tell you about this in brief

[@vlsiforrookies]

You can find the links in my channel's "about" section

[@iSeanx3]

Sadly I don't understand the language here :(