Verilog program to generate 1/2, 1/3 and 1/4 the frequency from the input clock.

Поделиться
HTML-код
  • Опубликовано: 28 окт 2024

Комментарии • 7

  • @JKECDURGESHKULAL
    @JKECDURGESHKULAL Год назад

    Nice explanation sir👍👏

  • @AmanKumar-ph4my
    @AmanKumar-ph4my 3 года назад +1

    nice one.. sir plz make more videos on verilog example .

  • @nl7966
    @nl7966 3 года назад

    what if we use non-blocking assignment to the b always block??

  • @mohitks62
    @mohitks62 3 года назад

    Pls make a video to implement a digital clock on seven segment display.

  • @ganauvm270
    @ganauvm270 3 года назад

    can you explain about dual clock fifo verilog code

  • @bhuvaneshm4607
    @bhuvaneshm4607 Год назад

    eyes are really burning useful content but cameraman doing overaction is not ok