Hi all, it never happens to me to see a sequence detector before, personally i would have suggest to embed some sort of "device id" approach, even if this implies having a dedicated id for each sub unit. Moreover, using a sequence detector could you possible have some strange situations in which the data stream you want to send to the subunit is seen by the sequence detector as a command regarding start and end stream, interrupting the process? Thanks for the video, could you suggest some book regarding basic "algorithms" and approaches in digital electronics, like the sequence detector you explained?
Hi Biswajit, Thank you for being a part of the community! We're trying our best to increase the frequency of uploads, we will probably be able to do so by the end of the year. If you can recommend us to your friends and colleagues it would be amazing!
Hi Divya, Thank you for your request! We will try our best to make a video about FPGA design in the coming weeks. If you can recommend us to your friends and colleagues it would be amazing!
Have a interview tomorrow at 1:30 to start an apprenticeship I really hope I can get into it it’s something I really want to learn and develope
great video, did he ever upload the solution to its following question? How do you design the circuit?
If this is an overlapping seq detector you only need s2 states. S2->S1 on a 1 output 1 or S0 for a 0.output 0.
And why the mux is a bad solution?
Takes a lot of space, also you need to route additional select bits for one data line.
Hi all, it never happens to me to see a sequence detector before, personally i would have suggest to embed some sort of "device id" approach, even if this implies having a dedicated id for each sub unit. Moreover, using a sequence detector could you possible have some strange situations in which the data stream you want to send to the subunit is seen by the sequence detector as a command regarding start and end stream, interrupting the process?
Thanks for the video, could you suggest some book regarding basic "algorithms" and approaches in digital electronics, like the sequence detector you explained?
Please make an explanation for Asynchronous FIFO as well.
Please increase the uploading frequency of the videos
Hi Biswajit,
Thank you for being a part of the community! We're trying our best to increase the frequency of uploads, we will probably be able to do so by the end of the year. If you can recommend us to your friends and colleagues it would be amazing!
Great video
Can you please put RF engineer related questions
Hi sir, can you put fpga design engineer questions.
Hi Divya,
Thank you for your request! We will try our best to make a video about FPGA design in the coming weeks. If you can recommend us to your friends and colleagues it would be amazing!
@@HardwareNinja do you already made that video?
4 flip flops --2 ^n =16 combinations
there are only 4 states so its two flops