Writing UVM/SystemVerilog Testbenches for Analog/Mixed-Signal Verification

[@akvmenon]

Thank you professor Charles for this detailed presentation. It clarified many of my questions on enabling a mixed signal simulation using uvm testbench and analog modelling tools.

[@AjayTumdam-m5o]

😊

[@stilingiceland1403]

Mixed language testbench is very challenge，thanks for the course

[@duongtrung2406]

thanks for the course