Back End Of Line : Part 2

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  • Опубликовано: 1 ноя 2024
  • Process steps involve in the back end of line of making a chip : contact plug, damascene process etc.

Комментарии • 12

  • @hninayemoe5880
    @hninayemoe5880 Год назад

    The explanation is very clear and precise . Exactly what I m looking for. Thank you 🙏

  • @RitishBehera-v9k
    @RitishBehera-v9k Год назад

    really impressed with explanation.very clear and precise with 3d schematics.Thank you for the series.

  • @changhung-wen22
    @changhung-wen22 3 года назад +1

    Thank you very much! The animation to introduce the process flow is very clear.

  • @ajikishaya463
    @ajikishaya463 2 года назад +1

    As perfect as this video may seem, it doesn't say anything on how the source and drain connect with gate which can create a endless loop of confusion: I saw an article that showed that the source-drain is not connected to its gate but a different gate in an undoped region. So what do you say concerning the gate in an undoped region?

  • @siddu47
    @siddu47 10 лет назад +1

    Thanks for nice video. I have 1 small query on this. Cu Seed layer (over the top of TaN) usually deposited through PVD technique right ? You mentioned it as CVD process. I would like to confirm on this..

  • @yanxiafeng5228
    @yanxiafeng5228 4 года назад

    Thank you so much. That's very helpful

  • @renqiu3449
    @renqiu3449 8 месяцев назад

    Crystal clear

  • @jigar__patel___
    @jigar__patel___ 6 лет назад

    In Finfet MEOL layer is introduced It will be great if you make video on why it is required those layer

  • @aishwaryanair7047
    @aishwaryanair7047 6 лет назад

    thanq so much sir. it was really helpful.