Thanks Zach I appreciated the more in-depth look at the solder and paste mask operation. A good video to consider would be to look at the different component layers used when creating or importing a new component and how these layers are displayed in the main PCB.
A quick little 3D peek at that last footprint on a board with the chip model suppressed (so we could see the paste and mask in relief) would have been great. Some of us can easily visualize the little blocks of solder within the pads of exposed copper surrounded by the tented vias, but others might need a visual aid. Edit: First?
if I want all routing vias to be tented, how to set up such a rule? provided I have another solder mask rule for all SMD pads with 2mil expansion (un-tented) as the first priority rule...I can't find an option to select things like "all SMT pads" or "all routing vias" to apply the two rules I am setting, end up always the first priority rule apply everything...
What you can do is create a top-priority rule and use the custom query IsVia to assign the rule only to vias, and then assign Tenting to this design rule. You can then create a separate rule for SMD pads using the IsSMTPin query, and another expansion rule for through-hole pads using the IsThruPin query. You can also create separate rules for different component classes or net classes, which is useful if for example you are using a higher density level on certain components.
@@Zachariah-Peterson Thank you so much for the information, do you have a video talking about how to place via in pad for BGA? how to set up such via in design rule?
Thanks Zach! This is the most complete video explaining about this subject, now I have understood exactly the meaning of this features.
Thanks Zach I appreciated the more in-depth look at the solder and paste mask operation. A good video to consider would be to look at the different component layers used when creating or importing a new component and how these layers are displayed in the main PCB.
A quick little 3D peek at that last footprint on a board with the chip model suppressed (so we could see the paste and mask in relief) would have been great. Some of us can easily visualize the little blocks of solder within the pads of exposed copper surrounded by the tented vias, but others might need a visual aid.
Edit: First?
Great video! Is there any rule (in design rules) to prevent too small a distance between two top solder pads?
if I want all routing vias to be tented, how to set up such a rule? provided I have another solder mask rule for all SMD pads with 2mil expansion (un-tented) as the first priority rule...I can't find an option to select things like "all SMT pads" or "all routing vias" to apply the two rules I am setting, end up always the first priority rule apply everything...
What you can do is create a top-priority rule and use the custom query IsVia to assign the rule only to vias, and then assign Tenting to this design rule. You can then create a separate rule for SMD pads using the IsSMTPin query, and another expansion rule for through-hole pads using the IsThruPin query. You can also create separate rules for different component classes or net classes, which is useful if for example you are using a higher density level on certain components.
@@Zachariah-Peterson Thank you so much for the information, do you have a video talking about how to place via in pad for BGA? how to set up such via in design rule?
@@sparklee6994 This video should help: ruclips.net/video/m_VxUKKUIk0/видео.html