Sam, your lectures are superb! Big thanks for posting! Would it be possible to make a follow-up where you go into the proper techniques of gate-drive, i particular when using a Kelvin connection to multi-source-pin FET device, and perhaps a bit about snubber network design and optimization?
Excellent summary. A further video detailing the Kelvin connection would be useful, one issue of interest is when using this connection is *not* beneficial, for example, when precise control over the di/dt during diode turn-off is required, in which case including source inductance in the gate drive circuit can be very helpful (I have seen extra intentional L added in the source lead for this specific purpose). The modern "super-junction" MOSFETs have parasitic capacitances that have a very strong voltage dependence which pose a challenge to optimise gate drive over the full range of operation (variations of duty-cycle, load current, and bus voltage); the effect of any inductance common to both source and gate drive currents can be very difficult to manage.
I wasn't exactly sure why Kelvin connections are good on some of these new-ish FETs but now I know ! I wonder some times though if just a 7 lead MOSFET can get the same effect by using one of those source leads for the kelvin connection just for the gate drive ? I know it would help with PCB inductance effects getting back into the driver but not sure exactly how the kelvin connections specifically built into FETs DIFFER from just the 7 lead style source connections that are there for lower RdsOn and lower inductance. Thanks for the great videos, Sam-Ben ! 😀😁
Dear Prof., First of all, amazing videos. Thank you for all the content. I would like to ask about the gate loop inductance effect... As we can see there are oscillations in Vgs. Now let's just consider one event, maybe turn off, (though similar thing can be considered for turn on too), we can see that when Vgs goes low, it undershoots and then overshoots until transient dies. I think first undershoot might be beneficial as it may discharge the capacitors quickly, but then first overshoot could be problematic as it could trigger spurious turn on of mosfet for a short time. (Please correct me if I'm wrong). So my question is, can we calculate the value of the overshoot and undershoot to see if it goes above Vth of mosfet to prevent spurious turn on by simple RLC circuit analysis in gate loop ( having gate loop inductance and Ciss in the loop)? The problem is that these capacitance values change with Voltage and also at the miller pletue, Cgs goes out of circuit... Hope this question is interesting for you. Thank you
Overshoots reach a max of twice the excitation for large Q, much larget than 1. For moderate Q= sqrt(L/C), the over/under shoot is per the second order transient respone.
Thank you Prof. May you please also answer the following: 1. Can you please suggest some literature that details calculation of overshoot and undershoot of gate voltage because of gate loop inductance. I'm interested in getting analytical solution to the peaks and the times ar which they occur. Also considering the miller pletue, how to analyse it for different times (i.e. does same 2nd order analysis thought the switching event or if we change the analysis method during miller pletue time and also when the difference parasitic capacitance values changes). 2. What would range of values would qualify as high Q, moderate Q and low Q. 3. Is voltage spike at Vgs always bad or can it be helpful too? Thank you again 😊
@@huanzhou4768 I think that what was meant by question is that the source pins include the Kelvin connections so there are more pins. But yes, using all the source pins will definitely lower the stray inductance and distribute the current between the pins ( one pin may not be able to carry a heavy current).
Thanks alot Professor for your lectures, I learn more from you than university,
😊🙏
Explaining convoluted transient behavior and their sources is fundamental for troubleshooting and HW robustness improvement. Thanks giving insight!
Thanks for comment
Thank you for the lecture. I keep learning new things from your lectures and gives me a new perspective to look at circuits
Thanks
All the best Prathamesh :P
at 16:20 what we see as disturbance on the blue signal is due to measurement device exactly because the Periode (T) of the disturbance is constant.
can you elaborate ?
But this could also be due to a parasitic resonant network.
Sam, your lectures are superb! Big thanks for posting!
Would it be possible to make a follow-up where you go into the proper techniques of gate-drive, i particular when using a Kelvin connection to multi-source-pin FET device, and perhaps a bit about snubber network design and optimization?
Thanks for suggestion David. Will consider it.
@@sambenyaakov yes sir please consider above ,I was also going to request same 😀
@@biswajit681 👍
@@sambenyaakov Me Too.
Excellent summary. A further video detailing the Kelvin connection would be useful, one issue of interest is when using this connection is *not* beneficial, for example, when precise control over the di/dt during diode turn-off is required, in which case including source inductance in the gate drive circuit can be very helpful (I have seen extra intentional L added in the source lead for this specific purpose). The modern "super-junction" MOSFETs have parasitic capacitances that have a very strong voltage dependence which pose a challenge to optimise gate drive over the full range of operation (variations of duty-cycle, load current, and bus voltage); the effect of any inductance common to both source and gate drive currents can be very difficult to manage.
Thanks for interesting input
You are my Master. Thank you and ask for more lessons.
😊🙏
Very good explanation! Thank you for making this video!
Thanks for coment
Great explanation, I’m struggling with 13.8V SMPS for HF ham radio to get rid of broadband noise, very disturbing.
Indeed, not simple in a radio
thank you for your lessons! very usefull to beginners!
Thanks
I wasn't exactly sure why Kelvin connections are good on some of these new-ish FETs but now I know !
I wonder some times though if just a 7 lead MOSFET can get the same effect by using one of those source leads for the kelvin connection just for the gate drive ? I know it would help with PCB inductance effects getting back into the driver but not sure exactly how the kelvin connections specifically built into FETs DIFFER from just the 7 lead style source connections that are there for lower RdsOn and lower inductance.
Thanks for the great videos, Sam-Ben ! 😀😁
" can get the same effect.." it is a question how the bonding is done and to where. Did you notice the large pointer ?😊
@@sambenyaakov I like large pointers ! You KNOW where it is ! 😁😀
Thank you so much, Professor.
Thanks
Dear Prof., First of all, amazing videos. Thank you for all the content.
I would like to ask about the gate loop inductance effect... As we can see there are oscillations in Vgs. Now let's just consider one event, maybe turn off, (though similar thing can be considered for turn on too), we can see that when Vgs goes low, it undershoots and then overshoots until transient dies. I think first undershoot might be beneficial as it may discharge the capacitors quickly, but then first overshoot could be problematic as it could trigger spurious turn on of mosfet for a short time. (Please correct me if I'm wrong).
So my question is, can we calculate the value of the overshoot and undershoot to see if it goes above Vth of mosfet to prevent spurious turn on by simple RLC circuit analysis in gate loop ( having gate loop inductance and Ciss in the loop)? The problem is that these capacitance values change with Voltage and also at the miller pletue, Cgs goes out of circuit...
Hope this question is interesting for you.
Thank you
Overshoots reach a max of twice the excitation for large Q, much larget than 1. For moderate Q= sqrt(L/C), the over/under shoot is per the second order transient respone.
Thank you Prof.
May you please also answer the following:
1. Can you please suggest some literature that details calculation of overshoot and undershoot of gate voltage because of gate loop inductance. I'm interested in getting analytical solution to the peaks and the times ar which they occur. Also considering the miller pletue, how to analyse it for different times (i.e. does same 2nd order analysis thought the switching event or if we change the analysis method during miller pletue time and also when the difference parasitic capacitance values changes).
2. What would range of values would qualify as high Q, moderate Q and low Q.
3. Is voltage spike at Vgs always bad or can it be helpful too?
Thank you again 😊
Very nice explanation
Thanks
Great video as always!
Thanks
The diode at 17:14 was across the source inductance, not the drain-source. An excellent lecture otherwise.
Thanks for noticing. I has evaded aa note n that at the RUclips page
Thank you so much sir
Thanks
Great
Thanks
Ah, that's why some mosfets have more source pins than drains!
Indeed
@@sambenyaakov You mean if we use more source pins, the stray inductance will be lower than only used one Source pin? Thanks Mr Ben Yaakov?
@@huanzhou4768 I think that what was meant by question is that the source pins include the Kelvin connections so there are more pins. But yes, using all the source pins will definitely lower the stray inductance and distribute the current between the pins ( one pin may not be able to carry a heavy current).
Great!
Thanks