FYI the on the last shot that has been left out, the low frequency cuttoff (-3dB) is measured at 12Hz which is much less than the required 100Hz design requirement. This shows the coupling and bypass capacitor design far exceeds the requirement.
You could use a single emitter resistor of 1K and let the emitter voltage be 0.5V. The resulting thermal drift of the collector current would be -2mV/1K per degC = -2μA per degC, which leads to a drift of +2μA x 15K = +30mV per degC. That's twice what your design has, but with far less complications and an extra 0.5V maximum swing. The gain would be 15K / (1K + 50R) = 14.3, which is less than 5% error and within likely component tolerances. If you're assuming β=100 (incidentally, not a good design since the minimum β for 2N4401 is actually about 30 at currents between 0.1mA and 1mA), then you can see that Ib = 5μA, so a parallel combination of 10K for R1 and R2 will drop only 5μA x 10k = 50mV (the Thevenin source times the current supplied) from whatever voltage the divider is set to. You already rounded Vbe up from 650mV to 700mV, which is a rounding error ten times the amount caused by this design having a higher base bias impedance than you specified. There's _no point_ in having 50 times the base current through the base bias network if the error it's trying to suppress (variations in β) is already ten times less than a rounding error you already made. In your design. the ac impedance looking into the base is β x (Re + re) = 100 x (820+50) = 87K. So the input impedance is 27K || 3.3K || 87k = 2.8K. it's as simple as that. You don't need hybrid-π or anything else. You just need to know that impedances in the emitter become β times larger in the base. The input coupling capacitor gives a -3dB point in the amplifier's frequency response when its reactance equals _the amplifier's input impedance._ The source resistance doesn't materially affect the -3dB frequency. So you need an input capacitor (C1) of 1 / (2π x 100Hz x 2.8K) = 0.57μF. Using a 1μF capacitor will give a -3dB point of 57Hz. Using your 22μF capacitor gives a -3dB point of 2.6Hz, which is a long way away from the design specification. Similarly for C2, the collector resistance does not significantly affect the -3dB frequency. For a 150K load, you need C2 = 1/(2π x 100Hz x 150K) = 10nF. You might have spotted that using 100μF is ludicrous and would result in a -3dB frequency of 0.01Hz. The RC time constant of 150K and 100μF is around 15 seconds and it would take around that length of time for the voltage across the 150K load to stabilise. For Ce, the base biasing has _no effect_ on the -3dB frequency. The gain is known to be Rc / (re + Re1 + (Xce || Re2)). That determines that the -3dB point occurs approximately when Xce = (re + Re1), which is 820+50 ohms in your design. So Ce = 1 / (2π x 100Hz x 820R) ≈ 2μF. It's a pity you didn't show the actual -3dB frequency for your circuit, as that would have made the point about correctly selecting capacitor values to match design specifications. Adding a 150K load to the output reduces the gain by the ratio 150K / (150K + 15K) = 0.91. That should reduce your calculated gain of 15K/870R = 17.2 down to 17.2 x 0.91 = 15.7. You measured 820mV/50mV = 16.4 - I don't know how you managed to get that equal to 15.7 at 31:24 perhaps you can re-check?
For the benefit of other viewers which calculations have mistakes? Also the method shown in the video is the most standard way to design common emitter amplifier. If you fast forward to the end my design method is confirmed with actual measurement. Thanks for stopping by!
@@SmithKerona Hi! First of all, thank you for the video, really helpful and I am having fun following along. Are you sure the C2 calculation is correct? I am getting 0,1 uF instead of 100 uF, am I interpreting something wrong or you left in a x1000 multiplier? Thank you in advance! EDIT: Nevermind, I kept watching the video and I saw you corrected it :P
FYI the on the last shot that has been left out, the low frequency cuttoff (-3dB) is measured at 12Hz which is much less than the required 100Hz design requirement. This shows the coupling and bypass capacitor design far exceeds the requirement.
This is outstanding, thank you. Really great walkthrough of the design and build. Look forward to more videos!
Very nice. Thanks.
You could use a single emitter resistor of 1K and let the emitter voltage be 0.5V. The resulting thermal drift of the collector current would be -2mV/1K per degC = -2μA per degC, which leads to a drift of +2μA x 15K = +30mV per degC. That's twice what your design has, but with far less complications and an extra 0.5V maximum swing. The gain would be 15K / (1K + 50R) = 14.3, which is less than 5% error and within likely component tolerances.
If you're assuming β=100 (incidentally, not a good design since the minimum β for 2N4401 is actually about 30 at currents between 0.1mA and 1mA), then you can see that Ib = 5μA, so a parallel combination of 10K for R1 and R2 will drop only 5μA x 10k = 50mV (the Thevenin source times the current supplied) from whatever voltage the divider is set to. You already rounded Vbe up from 650mV to 700mV, which is a rounding error ten times the amount caused by this design having a higher base bias impedance than you specified. There's _no point_ in having 50 times the base current through the base bias network if the error it's trying to suppress (variations in β) is already ten times less than a rounding error you already made.
In your design. the ac impedance looking into the base is β x (Re + re) = 100 x (820+50) = 87K. So the input impedance is 27K || 3.3K || 87k = 2.8K. it's as simple as that. You don't need hybrid-π or anything else. You just need to know that impedances in the emitter become β times larger in the base. The input coupling capacitor gives a -3dB point in the amplifier's frequency response when its reactance equals _the amplifier's input impedance._ The source resistance doesn't materially affect the -3dB frequency. So you need an input capacitor (C1) of 1 / (2π x 100Hz x 2.8K) = 0.57μF. Using a 1μF capacitor will give a -3dB point of 57Hz. Using your 22μF capacitor gives a -3dB point of 2.6Hz, which is a long way away from the design specification.
Similarly for C2, the collector resistance does not significantly affect the -3dB frequency. For a 150K load, you need C2 = 1/(2π x 100Hz x 150K) = 10nF. You might have spotted that using 100μF is ludicrous and would result in a -3dB frequency of 0.01Hz. The RC time constant of 150K and 100μF is around 15 seconds and it would take around that length of time for the voltage across the 150K load to stabilise.
For Ce, the base biasing has _no effect_ on the -3dB frequency. The gain is known to be Rc / (re + Re1 + (Xce || Re2)). That determines that the -3dB point occurs approximately when Xce = (re + Re1), which is 820+50 ohms in your design. So Ce = 1 / (2π x 100Hz x 820R) ≈ 2μF. It's a pity you didn't show the actual -3dB frequency for your circuit, as that would have made the point about correctly selecting capacitor values to match design specifications.
Adding a 150K load to the output reduces the gain by the ratio 150K / (150K + 15K) = 0.91. That should reduce your calculated gain of 15K/870R = 17.2 down to 17.2 x 0.91 = 15.7. You measured 820mV/50mV = 16.4 - I don't know how you managed to get that equal to 15.7 at 31:24 perhaps you can re-check?
Very helpful. Thank you
why in ac analysis you've placed Ce in series with Re?
Why are you dividing resistor values by (b+1) for Ce?
re'+Re*hfe= base input imp...
but in calculation you are using only re'+Re... not using hfe......is it correct..?😇
TO MANY CALCULATION MISTAKES AND, VERY DIFFICULT TO FOLLOW.I LEARNED HOW TO DO IT DIFFERENTLY COLLEGE.
For the benefit of other viewers which calculations have mistakes? Also the method shown in the video is the most standard way to design common emitter amplifier. If you fast forward to the end my design method is confirmed with actual measurement.
Thanks for stopping by!
@@SmithKerona
Hi!
First of all, thank you for the video, really helpful and I am having fun following along.
Are you sure the C2 calculation is correct? I am getting 0,1 uF instead of 100 uF, am I interpreting something wrong or you left in a x1000 multiplier?
Thank you in advance!
EDIT: Nevermind, I kept watching the video and I saw you corrected it :P