How to Design a sequential Circuit that Detects Three or More Consecutive 1's in the Input String?

correction:
0:32
In case of three or more consecutive 1's output is equal to 1
12:36
y is actually the AND of A and B

[@abener1013]

thank you very much

[@mushrifrila2632]

When it is pass input x=1,present state (10) to next state (11) its output should be 1 and
When it is pass x=0, present state (11) to next state (00) its output should be 0.
But in there you interchange this two.
Also in our university our lecturer also did the same.
But i dont know the reason why it is.
Could you please explain if there anything i miss or its a mistake of you

[@hebaatef3]

Same thing
Please if you know the correct answer say that

[@재돌-c2f]

your answer is correct. when 1 comes three times, output will be 1

[@mihiradeshappriya]

do you kno w how resolve this problem??

[@lamphuoclam424]

I think you're right, let me wait until tomorrow when I go to class, I will ask my teacher about this part.

[@mohammedsaleh5635]

the output(y) is moore output which means its a function of present state only so doing this state table of y is not 100% correct we should do a isolated table for y which include A(t) and B(t) only so when its 11 y became 1 the the sol in the video is wrong she builds a mealy diagram and did moore state table

[@f4fprinceyt202]

Tha last gate should be AND because there is A.B not A+B

[@eevibessite]

O yesss thanks for correction

[@SyedMuhammadAli-tr4cg]

what will be the input equations

[@eevibessite]

If you are asking for input equations of flip flop they are mentioned there. Since for a D flip flip whatever the input is transparent at the output.

[@نجمنجد-ض4ن]

Nah what is the sequence required to detect?

[@Music-w2t]

That Last part is Y=AB

[@sanskarsinghiit]

and for Db(second d-flip flop) there is no not gate to take complement of B, so Db is becoming Ax + Bx, and not Ax + B'x

[@ashishsavaratkar3418]

In mealy machine no of bits= number of states then why we take 4 states

[@PriyeshKJ]

state s2 and s3 are the same states with same outputs and final states with same inputs, although its way too late for the answer, ig

[@linonobre]

this circuit doesn't work for me...anybody simulated it?

[@eevibessite]

Did you implement it on hardware ?

[@linonobre]

@@eevibessite no, on simulator.

[@PriyeshKJ]

Also its equation not equaions

[@eevibessite]

Thanks dear....actually I make video in a single go so just the slipping of tongue

[@PriyeshKJ]

I was just joking ma'am. By the way video was quite helpful. Thanks a lot