One thing to note that the presentation does not make clear. You need a UVM Register Model, created, for example, by a model generator tool such as Cadence's reg_verifier from an IP-XACT register specification. This is important for addressing since, as descibed in the presentation, an absolute memory address is calculated from a base address supplied in a Register Model address map, and an offset address defined for a specific memory instance. The Register Model needs to be correctly integrated into your UVM testbench. Any memory instance in the model will then automatically have access to the Memory Manager. For more information on generating and integrating UVM Register Models, please search for the Cadence presentation "What is UVM Register Modelling?"
Hi, can you please explain what exactly is memory_4096_c ?
One thing to note that the presentation does not make clear. You need a UVM Register Model, created, for example, by a model generator tool such as Cadence's reg_verifier from an IP-XACT register specification. This is important for addressing since, as descibed in the presentation, an absolute memory address is calculated from a base address supplied in a Register Model address map, and an offset address defined for a specific memory instance.
The Register Model needs to be correctly integrated into your UVM testbench. Any memory instance in the model will then automatically have access to the Memory Manager.
For more information on generating and integrating UVM Register Models, please search for the Cadence presentation "What is UVM Register Modelling?"