VLSI design flow (Basics, Flowchart, Domains & Y Chart) Explained | VLSI by Engineering Funda

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  • Опубликовано: 5 окт 2024

Комментарии • 44

  • @EngineeringFunda
    @EngineeringFunda  11 месяцев назад +1

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  • @lifemotivation342
    @lifemotivation342 4 года назад +12

    u r God for electronics engineering student

  • @seanvai6476
    @seanvai6476 Год назад +5

    Your videos are truly a saviour when we fail to understand stuff at college. Thank you for making these. Keep up the good work. Im also an EC Engineering student. Thank you for these videos. Peace

    • @EngineeringFunda
      @EngineeringFunda  Год назад

      All the subjects playlist of Engineering Funda is available in comment section. Share it with your friends to support us.
      Your positive comments motivates me and person like me get boosted by my students feedback. Thanks and welcome 🙏

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  • @timholden1371
    @timholden1371 3 года назад +7

    Thank you for this video! I am a graduate student in a VLSI Design course at the moment, but due to the pandemic, labs are limited hindering some applications of the theoretical material covered outside of self-study. I will share your videos with my fellow students and once again thank you so much.

    • @EngineeringFunda
      @EngineeringFunda  3 года назад +1

      Your positive comments motivates me, Thanks and welcome 🙏

  • @saranyathanukkodi7674
    @saranyathanukkodi7674 4 года назад +7

    Thank u so much sir for making this videos it is very very useful for us

    • @EngineeringFunda
      @EngineeringFunda  4 года назад +3

      Your positive comments motivates me, Thanks and welcome 🙏

  • @AbhishekSingh0216
    @AbhishekSingh0216 3 года назад +5

    Thanku very much sir your videos are very useful especially for gtu exams .
    #Respect for you sir🙋‍♂️.

    • @EngineeringFunda
      @EngineeringFunda  3 года назад

      Your positive comments motivates me, Thanks and welcome 🙏

  • @rutvikjoshi4533
    @rutvikjoshi4533 4 года назад +7

    Sir you tough well but sir you can teach us with animation so will get more understanding about vlsi ,we will be learning vertuly as my perspective .thank you sir

    • @EngineeringFunda
      @EngineeringFunda  4 года назад

      Your positive comments motivates me, Thanks and welcome 🙏

  • @prabhavvyas3067
    @prabhavvyas3067 2 года назад +1

    Thank you so much sir for making this video

  • @roshanantony
    @roshanantony 3 года назад +1

    Hitesh bhai you are the best!!!

    • @EngineeringFunda
      @EngineeringFunda  3 года назад

      Your positive comments motivates me.
      Teachers like me just wants positive comment from student.
      Love from you guys means a lot to me.
      My goal is to create largest community of engineers in entire globe. Please help me by sharing this playlist with your friends.

  • @kirani.201
    @kirani.201 3 года назад +3

    Excellent sir 👍

    • @EngineeringFunda
      @EngineeringFunda  3 года назад +1

      Your positive comments motivates me, my goal is to create largest community of engineers in entire globe, so please help me for that by sharing this lecture series(playlist) with your friends in social media (watsapp, telegram etc). Thanks and welcome 🙏

    • @kirani.201
      @kirani.201 3 года назад +1

      Sir ur notes our clg lecture sharing with whole department ece excellent explaination

  • @vidheeshareddypemmana2670
    @vidheeshareddypemmana2670 4 года назад +2

    Useful sir, tq

    • @EngineeringFunda
      @EngineeringFunda  4 года назад +1

      Your positive comments motivates me. Thanks and welcome 🙏

  • @farhatmubeena7405
    @farhatmubeena7405 3 года назад +3

    Plz explain the topic of synthesis concept and logic synthesis concept in vlsi circuit

  • @SarvanCreation
    @SarvanCreation 3 года назад +1

    Good sir tq

    • @EngineeringFunda
      @EngineeringFunda  3 года назад

      Love and happiness of students is my ultimate goal, God bless you 🙏, keep learning and keep progressing.

  • @akashverma7205
    @akashverma7205 2 года назад +1

    best prereqvisit course for mtech freshar vlsi embedded students

    • @EngineeringFunda
      @EngineeringFunda  2 года назад

      Your positive comments motivates me.
      Teachers like me just wants positive comment from student.
      Love from you guys means a lot to me.
      My goal is to create largest community of engineers in entire globe. Please help me by sharing this playlist with your friends.

  • @03-ds-saipavan10
    @03-ds-saipavan10 2 года назад

    Your videos are Extraordinary sir...Thank you so much...Could you please tell the book you referred for VLSI?

  • @madhurinayini1562
    @madhurinayini1562 2 года назад +1

    mobile communication network video cheyra sir plz 18 r ece subject Plz dear 🥺

  • @nikunjvekariya4476
    @nikunjvekariya4476 4 года назад +1

    Good video full Course Na video uploaded karva helpful for EC STUDENTS

  • @dayamayan3893
    @dayamayan3893 2 года назад +1

    Can we consider this VLSI flow chart and explanation for R18 exams

  • @mohammedumarsheriff5801
    @mohammedumarsheriff5801 3 года назад

    i want to know why intel and amd does not use ball grid array on i3,5,7.. series.

  • @mohammedqamaruddin5693
    @mohammedqamaruddin5693 3 года назад +1

    ❤️❤️❤️❤️

    • @EngineeringFunda
      @EngineeringFunda  3 года назад

      Your positive comments motivates me.
      Teachers like me just wants positive comment from student.
      Love from you guys means a lot to me.
      My goal is to create largest community of engineers in entire globe. Please help me by sharing this playlist with your friends.

  • @uditpanchal6587
    @uditpanchal6587 3 года назад

    If This Question Will Ask in 7 Marks Then We Have To Describe the Y-Chart Or Not?

  • @shubhamraj9371
    @shubhamraj9371 Год назад

    Sir is it necessary or perquisites any coding languages to learn codings of vlsi lab? Or for learning whole vlsi

    • @EngineeringFunda
      @EngineeringFunda  Год назад

      Nope but alteast You should know python. As Industries needs few basic skills along Verilog.

  • @godofythandle
    @godofythandle 2 года назад

    Waste of time.