May be the values in waveform could be incorrect..but the concept was very clear which i believe the video is aimed at I'll try to summarize..Correct me if I'm wrong.. Launch means setting up the value at a gate output. Say for rise transition fault, the pin needs to be set to 0 initially as it requires 0 to 1 transition. This launch could be done on either Shift or Capture. In los, the setting up of initial value is done during scan shift itself. And when SE goes 0 right after the final shift clock and when capture pulse comes (at atspeed - after func clk time period), the opposite value will be injected during the capture pulse. SE neg edge needs to be constrained well for this as it needs to go low quickly and before capture pulse which comes at atspeed period ?? In the case of LOC, launch (setting up of value) is done during capture cycle itself (SE =0 ). This launch pulse can happen after many cycles after SE becomes 0. So SE timing may not be important here. After the initial value is set, the opposite value is injected by capture pulse spaced by atspeed clock period and the second flop captures the new value.
i think there is a small misunderstanding.. in example of rise fault. setting to 0 is initialization (not launch as u have mentioned). giving the input to the circuit to make the net 1 is the launch.
your shift register is not working properly if you are feeding 1011 value to the registers then scan enable waveform should be high, low, high,high.. and if you are feeding 1101 in registers then the input values at register should be .. please correct it
Hi Mallesh, one question...In LOC during second capture pulse why second scan flipflop value is not changing to 1 (during 1 capture pulse 1 will be available at Q of 1st flipflop which will be fed as D input to 2 flipflop for second capture pulse)
Hi hara gopal , data will moved from one flip flop to anothor flip flop only when scan_en is high, this is called shift mode .. when scan_en is made low and given a capture pulse .. the data will fed to only combinational logic part ..
@@malleshballa493 That is in the case of scan even though scan en is low when that 2nd second capture pulse happens, it will shift the logic value from the functional path where you have that And gate.
Hi Hara Gopal, While capture in LOC or LOS, scan flop capture the data from the combinational circuit to D path ,it should not be from the pervious scan flop Q. So, capture always depends on launch data(shift frequency SE =1 is LOC /at speed SE=0 is LOC) + combination circuit present b/w the scan flops
DFT is very tricky concept and difficult to grasp as in how it works on top level at the SOC …. so instead of some theoretically bookish language… try to build this concept in a very intuitive manner…..
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May be the values in waveform could be incorrect..but the concept was very clear which i believe the video is aimed at
I'll try to summarize..Correct me if I'm wrong..
Launch means setting up the value at a gate output. Say for rise transition fault, the pin needs to be set to 0 initially as it requires 0 to 1 transition. This launch could be done on either Shift or Capture.
In los, the setting up of initial value is done during scan shift itself. And when SE goes 0 right after the final shift clock and when capture pulse comes (at atspeed - after func clk time period), the opposite value will be injected during the capture pulse. SE neg edge needs to be constrained well for this as it needs to go low quickly and before capture pulse which comes at atspeed period ??
In the case of LOC, launch (setting up of value) is done during capture cycle itself (SE =0 ). This launch pulse can happen after many cycles after SE becomes 0. So SE timing may not be important here. After the initial value is set, the opposite value is injected by capture pulse spaced by atspeed clock period and the second flop captures the new value.
i think there is a small misunderstanding.. in example of rise fault. setting to 0 is initialization (not launch as u have mentioned). giving the input to the circuit to make the net 1 is the launch.
thanks for clearly giving info about launch, capture, los and loc.
Thanks for explaining so easy to understand!
Thanks. Nice explanation
your shift register is not working properly if you are feeding 1011 value to the registers then scan enable waveform should be high, low, high,high.. and if you are feeding 1101 in registers then the input values at register should be .. please correct it
Would you please give the reference for those circuit diagrams? From where you get those circuit diagrams to explain
Hi Mallesh,
one question...In LOC during second capture pulse why second scan flipflop value is not changing to 1 (during 1 capture pulse 1 will be available at Q of 1st flipflop which will be fed as D input to 2 flipflop for second capture pulse)
Hi hara gopal , data will moved from one flip flop to anothor flip flop only when scan_en is high, this is called shift mode .. when scan_en is made low and given a capture pulse .. the data will fed to only combinational logic part ..
@@malleshballa493 That is in the case of scan even though scan en is low when that 2nd second capture pulse happens, it will shift the logic value from the functional path where you have that And gate.
@hara gopal Yes I think, Yes you are right, the waveform for scan out needs to be modified.
Hi Hara Gopal,
While capture in LOC or LOS, scan flop capture the data from the combinational circuit to D path ,it should not be from the pervious scan flop Q. So, capture always depends on launch data(shift frequency SE =1 is LOC /at speed SE=0 is LOC) + combination circuit present b/w the scan flops
DFT is very tricky concept and difficult to grasp as in how it works on top level at the SOC …. so instead of some theoretically bookish language… try to build this concept in a very intuitive manner…..
sound is low. please be loud
Make some other video clearly and explain each and every wave form ur voice is very low not understand what ur saying...
Where z at speed clock??????
It is generated by system which is a separated clock wrt to scan_clk
video quality is very poor.