@@sarasajid1976 It makes no sense. A=1 means logic 1 i.e. HIGH. Your calculations of sizing are also incorrect. You are calculating for best case. Sizing is done for worst case
@@saadqayyum2148 I told you that for pull up network 1 doesn't means that it's value is 1 it's means it will in ON state. If all three will be ON than it gives you minimum resistance other wise it will give you maximum resistance . In case of 2 ON PULL UP R/2 In case of 1 ON PULL UP it will be R. Now you can get the idea in which case you will get a low resistance.
@@sarasajid1976 Moreover, your sizing calculation of 2/3 isn't correct. Please check Rabaey's book regarding sizing. Sizing cant be less than 1 because its with reference to a minimum sized NMOS, which is the smallest possible size in a given CMOS technology. With sizing of 2 for PMOS, the worst case resistance will be R and best case will be R/3.
Moreover, for sizing PUN and PDN, worst case is considered. Hence, sizing of PMOS will be 2 not 2/3. With sizing of 2 for PMOS, the worst case resistance will be R and best case will be R/3.
2:55 for A=B=C=1, none of the PMOS transistors will be on. PMOS turns on when input is 0
It doesn't mean that it has logic 1. It means that all the pull up transistor are ON
@@sarasajid1976 It makes no sense. A=1 means logic 1 i.e. HIGH. Your calculations of sizing are also incorrect. You are calculating for best case. Sizing is done for worst case
@@saadqayyum2148 I told you that for pull up network 1 doesn't means that it's value is 1 it's means it will in ON state. If all three will be ON than it gives you minimum resistance other wise it will give you maximum resistance .
In case of 2 ON PULL UP R/2
In case of 1 ON PULL UP it will be R.
Now you can get the idea in which case you will get a low resistance.
@@sarasajid1976 What you are saying is right but its not conventionally used.
@@sarasajid1976 Moreover, your sizing calculation of 2/3 isn't correct. Please check Rabaey's book regarding sizing. Sizing cant be less than 1 because its with reference to a minimum sized NMOS, which is the smallest possible size in a given CMOS technology. With sizing of 2 for PMOS, the worst case resistance will be R and best case will be R/3.
wonderfully explained
Moreover, for sizing PUN and PDN, worst case is considered. Hence, sizing of PMOS will be 2 not 2/3. With sizing of 2 for PMOS, the worst case resistance will be R and best case will be R/3.
For the worst -case of 3-input NAND gate, how many pmos are
_____?
one
Ma'am please share the notes of this video