Hi :) I recently started my journey into the design verification world. I got a job where I will be doing SystemVerilog for testbench in UVM (for ASICs), I was wondering if you have any tips so I can learn faster, so that I can go to big companies in 2/3 years?
very nice explanation and i really enjoyed it .
Glad you liked it!
bhaiya add more videos on system verilog. you are doing good. really enjoyed the video.
@@hackerorwhatt2284 sure bro working on it 😊
Hi :)
I recently started my journey into the design verification world. I got a job where I will be doing SystemVerilog for testbench in UVM (for ASICs), I was wondering if you have any tips so I can learn faster, so that I can go to big companies in 2/3 years?