great video. Any chance for you to go into more details on the wiring of the JTAG pins of the XC9572 to the platform USB box. I have about to do something very similar. I've a XC9572 in a PLCC44-to-DIP40 adapter and trying to workout which pins on to connect to the platform usb box to program it.
Sure, if you look at the datasheet of the Xilinx XC9572XL www.xilinx.com/support/documentation/data_sheets/ds057.pdf you'll find the pin number references on page 7
Thank you greatly for this how-to video. I'm exploring using the XC95__XL series (or the Coolrunner II) to sweep up some logic for a low volume/long lifetime design. I haven't programmed any CPLDs in the last couple decades, so it's been a trip down memory lane, mixed in with current OS and old/static design software interaction. Does anybody know of a software package that still takes schematic capture input for CPLD design??
Hey Shock, I’m looking to read the data that is already stored on to an XC9536 P44 CPLD that was on a failed IO device. I have two different Platform cables, 1 is a replica and the other is a cable directly from AMD (platform cable II). I just do not know how to write the code to get the software to read the device. Any tips on getting a read? Thanks!
I've not worked with used devices before. But I'm sure you'll need to make sure the security bit wasn't set in the initial programming first, or all you'll be reading out of those devices are zeros. ;-) If the security bit was _not_ set, then you should be able to read the previous programming using ISE Impact and its _Read Device_ function (presuming the drivers and your Windows setup are all worked out for your supported cable first). Hardest part is likely getting the cables working with Windows and Impact first. There are other tools that can read that device, but I've not used them.
@Drshock If you have several CPLD's in a chain connected to the same Jtac interface,- how do you select each one? I saw from your guide that a CPLD is show in the graphical interface .. would multiple CPLD just show up there? .. and you just select the right one?
I got ISE 14.7 running on Win10 x64 without problems. x32 files work out of the box but for the x64 files, it's about a minute of hacking. It took me a while to figure out but it's not very complicated actually when you know what you need to do.
for example, you can just double-click on the xise files, etc. I guess Xilinx is just trying to make it harder for people to use the previous generation of the toolchain.
At 3:50 I mention I am switching the UI to the _All Files_ view. What get's shown there are the source files for my Xilinx programming project. This segment is just showing that if you do not have the JEDEC file (the .jed file) from a third party github repo to use, you can rebuild that yourself using the Xilinx tooling. You need the .jed file to program the device.
To run ISE 14.7 (or earlier) on native Windows 10 without using a VM this is what you have to do: 1) Open the ISE installation folder i.e: C:\Xilinx\14.7\ISE_DS\ISE\lib t64 2) Find and rename libPortability.dll to libPortability.dll.bak 3) Make a copy of libPortabilityNOSH.dll in the same directory and rename the new file as libPortability.dll to replace the file in step 2. 4) Make a second copy of libPortabilityNOSH.dll but paste it into C:\Xilinx\14.7\ISE_DS\common\lib t64 5) Repeat step 2 by creating a backup of the libPortability.dll found in this folder. 6) Rename libPortabilityNOSH.dll to libPortability.dll Once this is done you should be able to run Xilinx ISE and Impact without issue on Windows without using a virtual machine.
I order a DLC9LP programmer from ali, but inside is a jtag smt2 pcb. I'm trying to write xc9572, but at 50% of witting i get programming failed. Is there any fix for that? Another issue is that when i use RUN ALL and after that i open impact, i have the oprions for erase, programm, etc, but If i open a jed file directly in impact (like you did in the video) all those commands are missing.
Yeah like I mention in the video, some of these clones deviate from the original Xilinx programming cable and they are just not reliable with the XC9500 series CPLDs. Diligent clones, etc they will all fail to verify where the _true_ DLC9LP clone will work fine. The eBay link I give in the description filters out those so you should only see the ones that will be compatible. I haven't seen an actual programming failure but rather verify failures, so your error may be something different.
I'm not familiar with that particular scope, but typically if you have a CPLD that needs replacing you'll have to be able to read the programming out of it first in order to program the replacement. The tools I've showed here can be used for that programming. However, most commercial vendors set the security bit on the XC9500 chips to prevent you from reading them. Technically only the original author of the firmware should be able to reprogram them, as they have the source code. So that's why Xilinx provides this security feature. You wouldn't know if Hantek set that bit without either some Google fu or trial and error.
No, there are several circuit board designs out there for these clone USB programming cables and they are not all compatible. So you have to use the drivers your seller should have provided when you bought it. Past that ISE will have the rest built-in.
For what it's worth, using a real Platform Cable USB II and a 64LQFP XC9572XL, I had a crazy problem where programmer and iMPACT would wind up locked up "The selected cable is being used by another application" with repeated: write count != nBytes(0), rc = 20000015. write cmd failed 20000015. write cmdbuffer failed 20000015. ...during "programming" step. Turns out, my hack of this part onto an existing PCB needed some more bypassing -- 0.1uF near every power pin "pair" and 2x 10uF. All ceramics X5R/X7R. Also, don't know if it mattered but I put a 0.1uF near power "Vref" pin going to programmer. (Go ahead, ask me why I'm putting a 1998 vintage part into a current production design in early 2022.)
hi. what's the difference between dlc9lp and dlc10. does it make sense to take dlc10, will there be any problems as in the case of jtag-smt2 and dlc9lp?
Either, though I haven't got around to testing it on my P500 yet. But it should replace both a MOS 6509 and 6509A. Works great on the B models, hats off to Go4Retro for the git submission
Great video! Just wondering if you have an email I can contact you with, regarding cpld programming....I don't know if what I want to do is even possible, you probably have more knowledge about it then I do
great video. Any chance for you to go into more details on the wiring of the JTAG pins of the XC9572 to the platform USB box. I have about to do something very similar. I've a XC9572 in a PLCC44-to-DIP40 adapter and trying to workout which pins on to connect to the platform usb box to program it.
Sure, if you look at the datasheet of the Xilinx XC9572XL www.xilinx.com/support/documentation/data_sheets/ds057.pdf you'll find the pin number references on page 7
Thank you for making this video. Helped me greatly.
Thank you greatly for this how-to video. I'm exploring using the XC95__XL series (or the Coolrunner II) to sweep up some logic for a low volume/long lifetime design. I haven't programmed any CPLDs in the last couple decades, so it's been a trip down memory lane, mixed in with current OS and old/static design software interaction.
Does anybody know of a software package that still takes schematic capture input for CPLD design??
Hey Shock, I’m looking to read the data that is already stored on to an XC9536 P44 CPLD that was on a failed IO device. I have two different Platform cables, 1 is a replica and the other is a cable directly from AMD (platform cable II).
I just do not know how to write the code to get the software to read the device.
Any tips on getting a read?
Thanks!
I've not worked with used devices before. But I'm sure you'll need to make sure the security bit wasn't set in the initial programming first, or all you'll be reading out of those devices are zeros. ;-) If the security bit was _not_ set, then you should be able to read the previous programming using ISE Impact and its _Read Device_ function (presuming the drivers and your Windows setup are all worked out for your supported cable first). Hardest part is likely getting the cables working with Windows and Impact first. There are other tools that can read that device, but I've not used them.
@Drshock If you have several CPLD's in a chain connected to the same Jtac interface,- how do you select each one? I saw from your guide that a CPLD is show in the graphical interface .. would multiple CPLD just show up there? .. and you just select the right one?
I've not had a circuit design with more than one, so not sure but I would suspect the ISE GUI would show them individually.
I got ISE 14.7 running on Win10 x64 without problems. x32 files work out of the box but for the x64 files, it's about a minute of hacking. It took me a while to figure out but it's not very complicated actually when you know what you need to do.
for example, you can just double-click on the xise files, etc. I guess Xilinx is just trying to make it harder for people to use the previous generation of the toolchain.
Lost me at 3:57. Where did all those files magically appear from?
At 3:50 I mention I am switching the UI to the _All Files_ view. What get's shown there are the source files for my Xilinx programming project. This segment is just showing that if you do not have the JEDEC file (the .jed file) from a third party github repo to use, you can rebuild that yourself using the Xilinx tooling. You need the .jed file to program the device.
To run ISE 14.7 (or earlier) on native Windows 10 without using a VM this is what you have to do:
1) Open the ISE installation folder i.e: C:\Xilinx\14.7\ISE_DS\ISE\lib
t64
2) Find and rename libPortability.dll to libPortability.dll.bak
3) Make a copy of libPortabilityNOSH.dll in the same directory and rename the new file as libPortability.dll to replace the file in step 2.
4) Make a second copy of libPortabilityNOSH.dll but paste it into C:\Xilinx\14.7\ISE_DS\common\lib
t64
5) Repeat step 2 by creating a backup of the libPortability.dll found in this folder.
6) Rename libPortabilityNOSH.dll to libPortability.dll
Once this is done you should be able to run Xilinx ISE and Impact without issue on Windows without using a virtual machine.
I order a DLC9LP programmer from ali, but inside is a jtag smt2 pcb. I'm trying to write xc9572, but at 50% of witting i get programming failed. Is there any fix for that? Another issue is that when i use RUN ALL and after that i open impact, i have the oprions for erase, programm, etc, but If i open a jed file directly in impact (like you did in the video) all those commands are missing.
Yeah like I mention in the video, some of these clones deviate from the original Xilinx programming cable and they are just not reliable with the XC9500 series CPLDs. Diligent clones, etc they will all fail to verify where the _true_ DLC9LP clone will work fine. The eBay link I give in the description filters out those so you should only see the ones that will be compatible. I haven't seen an actual programming failure but rather verify failures, so your error may be something different.
Cool video, I have an issue with XC95288XL on my hantek 2090 USB, is it replaceable ? thanks
I'm not familiar with that particular scope, but typically if you have a CPLD that needs replacing you'll have to be able to read the programming out of it first in order to program the replacement. The tools I've showed here can be used for that programming. However, most commercial vendors set the security bit on the XC9500 chips to prevent you from reading them. Technically only the original author of the firmware should be able to reprogram them, as they have the source code. So that's why Xilinx provides this security feature. You wouldn't know if Hantek set that bit without either some Google fu or trial and error.
@@DrShock I reckon, they will use the security bit, so I can not read it.
Hi! Is it necessary to erase then to program if the chip is not blank? any suggestions?
Best practice is to erase, just in case there is some residual data from a prior programming event that the new programming does not overwrite.
please how to debug the program from a cy37064p100 cpld by xilinx ise impact
Do you have a link to a copy of those Chinese drivers?
No, there are several circuit board designs out there for these clone USB programming cables and they are not all compatible. So you have to use the drivers your seller should have provided when you bought it. Past that ISE will have the rest built-in.
For what it's worth, using a real Platform Cable USB II and a 64LQFP XC9572XL, I had a crazy problem where programmer and iMPACT would wind up locked up "The selected cable is being used by another application" with repeated:
write count != nBytes(0), rc = 20000015.
write cmd failed 20000015.
write cmdbuffer failed 20000015.
...during "programming" step.
Turns out, my hack of this part onto an existing PCB needed some more bypassing -- 0.1uF near every power pin "pair" and 2x 10uF. All ceramics X5R/X7R.
Also, don't know if it mattered but I put a 0.1uF near power "Vref" pin going to programmer.
(Go ahead, ask me why I'm putting a 1998 vintage part into a current production design in early 2022.)
why ARE you putting a 1998 vintage part (the XC9572XL?) into a current production design in early 2022??
hi. what's the difference between dlc9lp and dlc10. does it make sense to take dlc10, will there be any problems as in the case of jtag-smt2 and dlc9lp?
Is this for a B or P series CBM?
Either, though I haven't got around to testing it on my P500 yet. But it should replace both a MOS 6509 and 6509A. Works great on the B models, hats off to Go4Retro for the git submission
Great video! Just wondering if you have an email I can contact you with, regarding cpld programming....I don't know if what I want to do is even possible, you probably have more knowledge about it then I do
Is this tool can read artix7
Thanks for the video. It is very helpful and straightforward.