Well said, Rick. PCB manufacturers are not fairy grandmothers or genies that can do what you want. They have fixed capabilities and PCB designers must work within their ranges to keep the board prices as low as possible.
I designed numerous boards since 2013, I never used 4 mil traces! At least for the majority of boards, 9 or 10 mils works just fine and it is manufacturable by all manufacturers I have seen so far. I can not imagine how these guys used 4 mil traces for normal no HDI PCBs.
1:18:50 Rick's comments on HDI stackups on Slide 26 don't seem to make sense to me. His slide 26 recommended stackup has sequential lamination: two laminations and two panel plating steps, which does add significant cost. But given that cost, I don't see why not add full thru-vias in this stackup. It seems that full thru-vias would get drilled and plated at the same time as plating the outer microvias, so it's just an extra drilling step, not another panel plating step? In fact, on the next slide, he says you can plate thru-vias at the same time as depth-controlled vias (although now showing just 1 lamination - I agree this is cheaper). Finally, the "extremely expensive" stackup on Slide 29, doesn't seem too bad, but yes it is 3 laminations when it could be 2 with a simple change: extend the middle blind via outwards one layer in each direction (L2:L7 instead of L3:L6). Then it's back to 2 laminations, which matches Rick's recommended stackup on Slide 26, just with both mechanical + laser drilling at each lamination instead of one or the other. @Zachariah-Peterson is there a reason on Slide 26 that thru vias add significant cost?
53:15 Eric Bogatin would argue that poring copper over the entire board is very silly. He claims (and shows with HFSS) that you get very little benefit from EMI and can easily make EMI much worse. When you have 2 of the biggest names in PCB engineering giving completely different answers it can be very difficult to know the correct solutions. In this case, I think Eric Bogatin has the correct information.
Eric and Rick are both correct in certain situations that do not always overlap. I've discussed why this is the case many times. Eric's advice is technically correct but it's easy to take out of context. Copper pour is one of those things that is sometimes presented as an "always/never" type of guidelines. The truth is that it has specific uses that are grounded in impedance controlled design and it's one of those things that some people do blindly without understanding those specific uses.
@@Zachariah-Peterson I'm currently confused about the idea of uneven copper pour causing issues with the plating process. I already watched that part of the video twice. According to this very presentation, it seems like the pattern plating happens *before* the outer layers are etched? So isn't the full board always covered with copper when the plating happens? Or was the idea of avoiding uneven copper fill specifically about the inner layers? If it was then I completely missed that point twice...
@maruohon I don't have time to watch the entire video now so I'm not sure which part you are referring to. But I know that the uneven copper can apply to outer or inner layers. The biggest reason is symmetry across the center of the stackup to prevent warping, which is less to do with plating and would apply to outer and inner layers. I have seen instances where there are exceptions, such as when the board is small and only 1 of the layers has a lot of its copper removed. The resulting warping would be very small and would be within IPC specs.
They are talking from 2 different POVs. Eric Bogatin is talking about using pours to help with EMI (often doesn't help much and can sometimes make it worse!) Rick Hartley is talking about manufacturing and assembly. Who cares the ingenious design you have if it can't be manufactured very well due to warpage? This is what Rick is trying to explain. I imagine that there is a nice medium between the 2 talking points, and Eric's points seem to be selected circumstances, but Zach already covered that I think.
@@alexanderquilty5705 Bogatin just talked about crosstalk avoidance in high speed signals: if you have space just do 5W or more without pour (makes things worse) if no space do the pour but with vias fence of the right spacing. All other pours are allowed for other things.
Why do we panelize boards if the fabricator will be distributing our design on the panel anyway? Do they not configure the design to be as optimal as personally laying out a panelized version?
@@alexanderquilty5705 They have become soo big and efficient that increasing layers, decreasing track size, color mask, etc, things don't affect price much, if at all, even for small orders. I took a freelance job recently shrinking a 4 layer single sided board and comverted it to 6 layer double sided assembly and the price jump wasn't bank breaking.
Why don't the fabricators create the thief dots for the plating process and then just etch them away later? It would still obviously be more costly and a sub-optimal design. Just trying to satisfy a curiosity rather than disagree with the overall message.
He says he has 6 or 8 hours of content, then proceeds to give you 30 min of information in 1.5 hours. The stories and facts are great, but a lot of what he says is just repeating himself.
![[LIVE] How to Achieve Proper Grounding - Rick Hartley - Expert Live Training (US)](http://i.ytimg.com/vi/ySuUZEjARPY/mqdefault.jpg)
![[LIVE] How to Achieve Proper Grounding - Rick Hartley - Expert Live Training (US)](/img/tr.png)
Rick's voice is music to my years which directly touches my heart and brain at same time
Have you watched Breaking Bad / Better Call Saul? Because he sounds exactly like Mike Ehrmantraut. Who also sounds like music to my ears.
When Rick talks you just listen, he has a good way of communicating knowledge
Great presentation with an incredible amount of insight and knowledge. Rick is the best!
Well said, Rick. PCB manufacturers are not fairy grandmothers or genies that can do what you want. They have fixed capabilities and PCB designers must work within their ranges to keep the board prices as low as possible.
I designed numerous boards since 2013, I never used 4 mil traces! At least for the majority of boards, 9 or 10 mils works just fine and it is manufacturable by all manufacturers I have seen so far. I can not imagine how these guys used 4 mil traces for normal no HDI PCBs.
We use 2 mils all the time.
Great interesting lecture by the Mike Ehrmantraut of PCB design.
Glad you liked it!
great content and great presentation.
very informative , thank u , you really change the way we think about circuit design , We want more !! :)
1:18:50 Rick's comments on HDI stackups on Slide 26 don't seem to make sense to me. His slide 26 recommended stackup has sequential lamination: two laminations and two panel plating steps, which does add significant cost. But given that cost, I don't see why not add full thru-vias in this stackup. It seems that full thru-vias would get drilled and plated at the same time as plating the outer microvias, so it's just an extra drilling step, not another panel plating step? In fact, on the next slide, he says you can plate thru-vias at the same time as depth-controlled vias (although now showing just 1 lamination - I agree this is cheaper). Finally, the "extremely expensive" stackup on Slide 29, doesn't seem too bad, but yes it is 3 laminations when it could be 2 with a simple change: extend the middle blind via outwards one layer in each direction (L2:L7 instead of L3:L6). Then it's back to 2 laminations, which matches Rick's recommended stackup on Slide 26, just with both mechanical + laser drilling at each lamination instead of one or the other.
@Zachariah-Peterson is there a reason on Slide 26 that thru vias add significant cost?
53:15 Eric Bogatin would argue that poring copper over the entire board is very silly. He claims (and shows with HFSS) that you get very little benefit from EMI and can easily make EMI much worse. When you have 2 of the biggest names in PCB engineering giving completely different answers it can be very difficult to know the correct solutions. In this case, I think Eric Bogatin has the correct information.
Eric and Rick are both correct in certain situations that do not always overlap. I've discussed why this is the case many times.
Eric's advice is technically correct but it's easy to take out of context. Copper pour is one of those things that is sometimes presented as an "always/never" type of guidelines. The truth is that it has specific uses that are grounded in impedance controlled design and it's one of those things that some people do blindly without understanding those specific uses.
@@Zachariah-Peterson I'm currently confused about the idea of uneven copper pour causing issues with the plating process. I already watched that part of the video twice. According to this very presentation, it seems like the pattern plating happens *before* the outer layers are etched? So isn't the full board always covered with copper when the plating happens? Or was the idea of avoiding uneven copper fill specifically about the inner layers? If it was then I completely missed that point twice...
@maruohon I don't have time to watch the entire video now so I'm not sure which part you are referring to. But I know that the uneven copper can apply to outer or inner layers. The biggest reason is symmetry across the center of the stackup to prevent warping, which is less to do with plating and would apply to outer and inner layers. I have seen instances where there are exceptions, such as when the board is small and only 1 of the layers has a lot of its copper removed. The resulting warping would be very small and would be within IPC specs.
They are talking from 2 different POVs. Eric Bogatin is talking about using pours to help with EMI (often doesn't help much and can sometimes make it worse!)
Rick Hartley is talking about manufacturing and assembly. Who cares the ingenious design you have if it can't be manufactured very well due to warpage? This is what Rick is trying to explain. I imagine that there is a nice medium between the 2 talking points, and Eric's points seem to be selected circumstances, but Zach already covered that I think.
@@alexanderquilty5705 Bogatin just talked about crosstalk avoidance in high speed signals: if you have space just do 5W or more without pour (makes things worse) if no space do the pour but with vias fence of the right spacing. All other pours are allowed for other things.
Hey Rick can we get a HD picture of your bookshelf?😂
I like this better. He reads all books and give us the summary 😊
Rupal M hahahahaha remembering high scool
Would you please make the slides available?
Why do we panelize boards if the fabricator will be distributing our design on the panel anyway? Do they not configure the design to be as optimal as personally laying out a panelized version?
Thanks Rick.
Wow, PCB fabrication is more complicated than PCB EMC.
JLCPCB be pissing over all of this video
Is their process very different?
@@alexanderquilty5705 They have become soo big and efficient that increasing layers, decreasing track size, color mask, etc, things don't affect price much, if at all, even for small orders.
I took a freelance job recently shrinking a 4 layer single sided board and comverted it to 6 layer double sided assembly and the price jump wasn't bank breaking.
@@alexanderquilty5705trial and error 😅
nice
like it 👍
Why don't the fabricators create the thief dots for the plating process and then just etch them away later? It would still obviously be more costly and a sub-optimal design. Just trying to satisfy a curiosity rather than disagree with the overall message.
He says he has 6 or 8 hours of content, then proceeds to give you 30 min of information in 1.5 hours. The stories and facts are great, but a lot of what he says is just repeating himself.
annoying as hell... "I'll tell you later" .... grrrrrrr
Amazing, just amazing!