Due to pipelining, the PC should be pointing on the next line in the drawing...at least that's how it is on ARM9. I believe it's the same on the Cortex. Can easily be proved by checking the listing and see what offset the assembler puts.
Why the address increases by 4? Does it means every memory segment have 4 bytes(8bit hexadecimal number or 32bit binary number) of data? So is the address means how many bytes?
In the section on Literal Pooling, we don't finally use the Jenny label to reference the constant stored in 'another' file, but we use the PC and declare the 32-bit constant at the end of the subroutine, in the same file, as the LDR instruction needs a register to provide a source memory address. Is it thus not possible to use the method that dealt with the Jenny label with the LDR command?
+Aditya Kapoor I don't quite follow your question... The Jenny constant is _defined_ in another _source_ file, but assembler reserves space for it in the literal pool whenever we use it as a literal operand. Finally, the linker will insert the actual _value_ of Jenny into the _object_ file after all of the modules are assembled. With literal addressing the register that provides the source memory address is the PC, with an offset applied to access something in the literal pool.
Thanks a ton "JoeTheProfessor" for posting this video. The whole thing about Literal Pool was driving me crazy. Your video has simplified it. I have one more question on "The Cortex-M0 processor supporting immediate offset addressing modes". It is denoted as: LDR , [, #immed5] ; Word read Does "#immed5" mean that the "Offset" can only be 5 bits long(32 bytes). If "yes", does this restriction again come due to limited size of the instruction??
Yes, the size of the instruction encoding limits how many bits can be used for the immediate value and the M0 doesn't support all of the 32-bit instructions available on the M3 and M4. However, when the LDR instruction is used for the literal addressing mode we know that Rn is going to be the PC so the instruction encoding doesn't need to reserve bits to specify Rn. That means that the LDR literal instruction can allow a larger immediate value than the more general LDR immediate offset instruction.
LDR R0, =JENNY ; this will load the memory address of the JENNY constant in the R0. LDR R1, [R0] ; this will load the value from the memory address where JENNY constant is present into R1 // What is shown in literal addressing (10:40) will store the address of the count in the R0, not the content (0x00845FED) as shown.
No, the actual value of JENNY gets loaded into R0. We don't need to load a full 32-bit address for JENNY into a register because JENNY is stored very close to the code, in the literal pool. The LDR instruction can use a short offset from the PC as a literal value that is embedded in the instruction encoding. This only works if the value we want to load is a constant that the linker can place in the literal pool...what you say is correct for values at arbitrary memory locations, such as hardware registers.
I am taking Embedded system course (UTAustin), what I have learnt. (Introduction to ARM Cortex-M controller, Jonathan W. Valvano text book) LDR R0, =JENNY ; R0 points to variable JENNY , PC- relative LDR R1,[R0] ; R1= value pointed to by R0 R0,=JENNY makes R0 equal to 0x20000000 (assume 0x2000.0000 is the address where JENNY is placed) i.e R0 points to JENNY. The assembler places a constant 0x20000000 in code space and translate the =JENNY into correct PC-relative access to the constant (LDR R0, [PC, #24]). In this case, the constant 0x20000000, the address of count, will be located at PC+24. Second, LDR R1,[R0] instruction will dereference this pointer, bringing 32-bit contents at location 0x20000000 into R1. Since JENNY is located at 0x20000000, these two instruction will read the value of JENNY into R1. Keil Assembler user guide, The LDR Rd,=label pseudo-instruction places an address in a literal pool and then loads the address into a register. www.keil.com/support/man/docs/armasm/armasm_dom1359731149945.htm
Sorry, but there is a subtle difference that the Valvano course must not have clarified. If the data we really want to get is a CONSTANT then the data itself will be stored in the literal pool. So, JENNY is NOT stored at 0x2000000 (RAM) it is stored in the program memory (specifically in the literal pool), usually just after the function code that needs it. Therefore, we just need one LDR to get the actual constant value into a register. The situation you are talking about is different...in that case the data we want is in RAM or a peripheral register. In this case, as you say, the ADDRESS of the data will be stored in the literal pool and we need two LDR instructions to get the actual data: one to get the address of the data and the other to use that address to get the actual data. The crucial difference is that JENNY in my example is a constant value that is never stored in RAM.
It can be a data or an address or an offset to an address depending on how it is used: Used as a data: ADDS R1, R0 Used as an address (1st parameter inside the bracket,). In this case, it is a pointer (just like the pointer in C. LDR R1, [R0] Used as an offset (2nd parameter inside the bracket): LDR R1, [R2, R0]
If a full 32-bit address cannot be used in an instruction, couldn't the same be said about registers? Because, you know, that pointer value must have gotten to that register in some way, and it is a 32-bit value either way, right?
The issue is that we can't embed a 32-bit value as part of an instruction encoding. If we want to load a specific arbitrary 32-bit value into a register we need either two instructions, a MOVW and a MOVT, that are each 32 bits, or we can use an LDR instruction with the literal addressing mode and have the 32-bit constant stored in program memory (the literal pool).
@@joetheprofessor6260 Yes, I know. My point was that it's a bit like a weird chicken & egg problem with the ISA design itself: you can't tell the 32-bit address directly as an operand, but you can use a 32-bit register. But in order to set that 32-bit register, you have to use TWO instructions and jump through hoops to make it work. It doesn't take less space to do so, neither is it faster, nor easier to program, so what's the point? :q Wouldn't it be easier to just have that 32-bit address as an operand in the very next 32-bit word after the instruction? Then it would take onlu 64 bits total, instead of at least 3 instructions (MOVW, MOVT, and the one that uses the address), which is 3×32-bit = 96 bits already :q
If you have some instructions that include a 32-bit value right after the instruction, but many instructions that do not, then you no longer have a RISC architecture. Instruction decoding, pipelining, and branch prediction become much more complicated, thus slowing down the execution of every instruction. If you only load a full 32-bit constant occasionally it is better to use a couple of fast instruction to do it rather than slow down the whole processor.
i have a question about armv7-m arch does it support harvard or Vonnuman i really need answer to this question because in the first video it seems like vonNuman but in the referance manual for armv7-m it says its harvard.
I would say that the armv7-m architecture combines the best of both styles. The physical architecture provides separate access paths for the instruction memory and the data memory, which generally improves performance. However, both of these memories are mapped into the same address space and can be accessed with the same instructions, and it is possible to execute programs from data memory or store data in instruction memory. I think the only downside is that there may be a loss of throughput (i.e. increased execution time) if you try to run code from the data space or store lots of data in the instruction memory...it would depend upon how the processor prefetches or caches access to each space.
You can use immediate addressing in a limited way. You can use an immediate operand to specify an offset from the address contained in a register, which is basically what the literal addressing mode does. There are variations where the immediate value is then added to the value in the register that holds the address, so you can step through elements of an array. I'm not sure what you mean by relative addressing...in a sense the LDR and STR are always "register relative".
@@kennethhass1647 I'm just giving exams on a subject in September whose name is microprocessors and the proffeseur puts an exercise on style multiple choice.also a question from the exams will be like these.do load / store type commands use indirect, immediate or relative addressing? i still have a question if you can answer me;Raid 0 used for applications where lower cost or capacity has biggest priority?could you answer on those questions please.i really need help.
@@joetheprofessor6260 is there any platform where we could buy your ARM course? Your teaching way is impressed me.Thank you so much.You are one of the best tutors that i have seen
Registers are not in the memory so they do not have memory addresses. Probably in some cases a register has a memory address, but not in ARM processors.
Many of these videos about ARM are so abstract that they are useless. Your videos are very good and to the point. Thank you for your work.
The fact that this level of content is available for free on the internet is astonishing.
Ladies and Gentlemen I feel like i owe Joe The Professor for this job. This is pure gold
You are a lifesaver Professor Joe
I’m guessing that your videos are about to get a whole lot more popular.
This helped a lot for my assembly language class thank you.
Thank you for these videos, are well explained.
You are the hero we needed
Tommy Tutone is now stuck in my head, thank you.
very rich illustration. Thanx indeed.
Great videos, very helpful in understanding basic assembly coding.
Due to pipelining, the PC should be pointing on the next line in the drawing...at least that's how it is on ARM9. I believe it's the same on the Cortex. Can easily be proved by checking the listing and see what offset the assembler puts.
thanks a lot Joe
what is difference between memory and address...??
thank you sir for very smooth explanation
great video sir
It hepls much, thank you
Thank you so much for the video.
best video i agree with this
excellent videos, thanks a lot and congrats
great video, thank you!
Brilliant!
Joe = King
Why the address increases by 4? Does it means every memory segment have 4 bytes(8bit hexadecimal number or 32bit binary number) of data? So is the address means how many bytes?
Thank you so much
good stuff
In the section on Literal Pooling, we don't finally use the Jenny label to reference the constant stored in 'another' file, but we use the PC and declare the 32-bit constant at the end of the subroutine, in the same file, as the LDR instruction needs a register to provide a source memory address. Is it thus not possible to use the method that dealt with the Jenny label with the LDR command?
+Aditya Kapoor I don't quite follow your question... The Jenny constant is _defined_ in another _source_ file, but assembler reserves space for it in the literal pool whenever we use it as a literal operand. Finally, the linker will insert the actual _value_ of Jenny into the _object_ file after all of the modules are assembled. With literal addressing the register that provides the source memory address is the PC, with an offset applied to access something in the literal pool.
Tnx
Fuck yeah, amazing tutorial
THANK YOU!!!!!!!!!!!!!!!
thanks a lot man
amazing
no mention of LDRB and LDRH
Thanks a ton "JoeTheProfessor" for posting this video. The whole thing about Literal Pool was driving me crazy. Your video has simplified it. I have one more question on "The Cortex-M0 processor supporting immediate offset addressing modes". It is denoted as:
LDR , [, #immed5] ; Word read
Does "#immed5" mean that the "Offset" can only be 5 bits long(32 bytes). If "yes", does this restriction again come due to limited size of the instruction??
Yes, the size of the instruction encoding limits how many bits can be used for the immediate value and the M0 doesn't support all of the 32-bit instructions available on the M3 and M4. However, when the LDR instruction is used for the literal addressing mode we know that Rn is going to be the PC so the instruction encoding doesn't need to reserve bits to specify Rn. That means that the LDR literal instruction can allow a larger immediate value than the more general LDR immediate offset instruction.
JoeTheProfessor ..... Thank you Prof. It is clear now. Hoping to see more of your ARM videos coming in future. Once again.... Thanks!!
LDR R0, =JENNY ; this will load the memory address of the JENNY constant in the R0.
LDR R1, [R0] ; this will load the value from the memory address where JENNY constant is present into R1
// What is shown in literal addressing (10:40) will store the address of the count in the R0, not the content (0x00845FED) as shown.
No, the actual value of JENNY gets loaded into R0. We don't need to load a full 32-bit address for JENNY into a register because JENNY is stored very close to the code, in the literal pool. The LDR instruction can use a short offset from the PC as a literal value that is embedded in the instruction encoding. This only works if the value we want to load is a constant that the linker can place in the literal pool...what you say is correct for values at arbitrary memory locations, such as hardware registers.
I am taking Embedded system course (UTAustin), what I have learnt. (Introduction to ARM Cortex-M controller, Jonathan W. Valvano text book)
LDR R0, =JENNY ; R0 points to variable JENNY , PC- relative
LDR R1,[R0] ; R1= value pointed to by R0
R0,=JENNY makes R0 equal to 0x20000000 (assume 0x2000.0000 is the address where JENNY is placed) i.e R0 points to JENNY. The assembler places a constant 0x20000000 in code space and translate the =JENNY into correct PC-relative access to the constant (LDR R0, [PC, #24]). In this case, the constant 0x20000000, the address of count, will be located at PC+24. Second, LDR R1,[R0] instruction will dereference this pointer, bringing 32-bit contents at location 0x20000000 into R1. Since JENNY is located at 0x20000000, these two instruction will read the value of JENNY into R1.
Keil Assembler user guide, The LDR Rd,=label pseudo-instruction places an address in a literal pool and then loads the address into a register. www.keil.com/support/man/docs/armasm/armasm_dom1359731149945.htm
Sorry, but there is a subtle difference that the Valvano course must not have clarified. If the data we really want to get is a CONSTANT then the data itself will be stored in the literal pool. So, JENNY is NOT stored at 0x2000000 (RAM) it is stored in the program memory (specifically in the literal pool), usually just after the function code that needs it. Therefore, we just need one LDR to get the actual constant value into a register.
The situation you are talking about is different...in that case the data we want is in RAM or a peripheral register. In this case, as you say, the ADDRESS of the data will be stored in the literal pool and we need two LDR instructions to get the actual data: one to get the address of the data and the other to use that address to get the actual data. The crucial difference is that JENNY in my example is a constant value that is never stored in RAM.
So does it mean for let's say r0 which contains 0x00000011, 0x00000011 can be either a memory or an address?
It can be a data or an address or an offset to an address depending on how it is used:
Used as a data:
ADDS R1, R0
Used as an address (1st parameter inside the bracket,). In this case, it is a pointer (just like the pointer in C.
LDR R1, [R0]
Used as an offset (2nd parameter inside the bracket):
LDR R1, [R2, R0]
If a full 32-bit address cannot be used in an instruction, couldn't the same be said about registers? Because, you know, that pointer value must have gotten to that register in some way, and it is a 32-bit value either way, right?
The issue is that we can't embed a 32-bit value as part of an instruction encoding. If we want to load a specific arbitrary 32-bit value into a register we need either two instructions, a MOVW and a MOVT, that are each 32 bits, or we can use an LDR instruction with the literal addressing mode and have the 32-bit constant stored in program memory (the literal pool).
@@joetheprofessor6260 Yes, I know. My point was that it's a bit like a weird chicken & egg problem with the ISA design itself: you can't tell the 32-bit address directly as an operand, but you can use a 32-bit register. But in order to set that 32-bit register, you have to use TWO instructions and jump through hoops to make it work. It doesn't take less space to do so, neither is it faster, nor easier to program, so what's the point? :q Wouldn't it be easier to just have that 32-bit address as an operand in the very next 32-bit word after the instruction? Then it would take onlu 64 bits total, instead of at least 3 instructions (MOVW, MOVT, and the one that uses the address), which is 3×32-bit = 96 bits already :q
If you have some instructions that include a 32-bit value right after the instruction, but many instructions that do not, then you no longer have a RISC architecture. Instruction decoding, pipelining, and branch prediction become much more complicated, thus slowing down the execution of every instruction. If you only load a full 32-bit constant occasionally it is better to use a couple of fast instruction to do it rather than slow down the whole processor.
Actually sir..u got quite good no. of followers.. why don't u do more of these
i have a question about armv7-m arch does it support harvard or Vonnuman i really need answer to this question because in the first video it seems like vonNuman but in the referance manual for armv7-m it says its harvard.
I would say that the armv7-m architecture combines the best of both styles. The physical architecture provides separate access paths for the instruction memory and the data memory, which generally improves performance. However, both of these memories are mapped into the same address space and can be accessed with the same instructions, and it is possible to execute programs from data memory or store data in instruction memory. I think the only downside is that there may be a loss of throughput (i.e. increased execution time) if you try to run code from the data space or store lots of data in the instruction memory...it would depend upon how the processor prefetches or caches access to each space.
thx a lot about ur fast replay it is clearly now for me how it works..
hope to see more videos of such a kind
One question.we can use immediate addressing and relative addressing on instructions load /store?
You can use immediate addressing in a limited way. You can use an immediate operand to specify an offset from the address contained in a register, which is basically what the literal addressing mode does. There are variations where the immediate value is then added to the value in the register that holds the address, so you can step through elements of an array. I'm not sure what you mean by relative addressing...in a sense the LDR and STR are always "register relative".
@@kennethhass1647 I'm just giving exams on a subject in September whose name is microprocessors and the proffeseur puts an exercise on style multiple choice.also a question from the exams will be like these.do load / store type commands use indirect, immediate or relative addressing? i still have a question if you can answer me;Raid 0 used for applications where lower cost or capacity has biggest priority?could you answer on those questions please.i really need help.
at 4:50, What would be the difference if you had wrote “LDR R6, [R1,#4]” instead of “LDR R6,[R1,4]”?
Would that have loaded what is at R5 into R6 instead of what is at 0x00A4?
I think these are the same instructions with just different syntax for different assemblers.
@@joetheprofessor6260 can you provide link to your website?
@@joetheprofessor6260 is there any platform where we could buy your ARM course? Your teaching way is impressed me.Thank you so much.You are one of the best tutors that i have seen
what about multiple load and store
how can i Write value 0x12345678 into RAM memory location 0x20000000 using ARM assembler.
LDR R0, =0x12345678
LDR R1, =0x20000000
STR R0, [R1, #0] ; or can be written as STR R0, [R1]
4:00 man, why the register has not address?
It has.
Registers are not in the memory so they do not have memory addresses. Probably in some cases a register has a memory address, but not in ARM processors.
@@chewey Technically, r0 is the first register so it is an address in the CPU's small RAMs...r1 the 2nd...etc.
Is professor Joe actually Joe Armstrong? It's such a pity he passed away Apr 2019. I hope he's NOT. Your videos are quite good!
No, I'm still here.
@@joetheprofessor6260 Glad to know that! Welcome to generate more videos!
Could you please add english subtitles it would be then much more clearer . Thank you very much.
)))
Thanks so much