This is an excellent series. I like the video format because I can pause and work through the math and graphs to solidify the concepts in my head before moving on. Thank you for taking the time to create these.
Thank you very much Prof Sam Ben-Yakoov for these fascinating deep insights.Controlling a power mosfet, seems like riding a wild horse. Very hard, but possible due to your excellent explanations.
Practical case about peak Vgs voltage holding if anyone is interested Setup: IMBF170R1K0M1 SiC-FET (20 Vgs according to datasheet) acting as a switch, drived via the KSP2222 BJT in avalanche mode. No TVS or Zenner connected to g-s. Mosfet holds a 120 Vp pulse on gate with 1.5 ns rise-time and 30 ns duration. Current pulse rise in the drain-load loop is about 2 ns. No gate breakdowns occured after many hours of working. The duration of the applied pulse has a great importance. At more classical timing, like 1-10 uS pulse, gate breakdown occurs at 40-50 V already.
@@sambenyaakov No, the manufacturer avoids mentioning such modes for commercial risks reasons. As one engineer from Wolfspeed told me once - “We define values in the datasheets that we can guarantee based on data from our development and testing department. They are often underestimated, but still ensure a minimum number of failures. You can work above these limits - but this at your own risk, and we decline our liability in such cases." I should probably warn those who read the previous message - if you are developing commercial electronics, do not go beyond the datasheet limits, otherwise you may incur serious costs. The case I described is purely laboratory-experimental, just to keep in mind. Good for IEEE/ResearchGate articles, but not for the market.
The total energy the transistor dissipates is the inductor's stored energy PLUS the additional energy provided by the battery while the current is flowing. Given the two battery analogy, the left battery is charged while the right battery is discharged. The energy delivered by the battery is VIt/2... its voltage times the average current times the time to discharge the inductor.
This is correct but has been taken into account in the derivation. And if you missed this: no matter from where the current is coming, the energy absorbed by the transistor is always Q*Vbr.
@@biswajit681 Have you seen this? Also intersting www.linkedin.com/posts/ben-yaakov-shmuel-sam-49094422_pop-quiz-what-is-this-circuit-extra-credit-activity-7184221013507772416-u5_u?
This is an excellent series. I like the video format because I can pause and work through the math and graphs to solidify the concepts in my head before moving on. Thank you for taking the time to create these.
Thanks for note and sharing.
Thank you very much Prof Sam Ben-Yakoov for these fascinating deep insights.Controlling a power mosfet, seems like riding a wild horse. Very hard, but possible due to your excellent explanations.
Thank you, I appreciate it. Comments like yours keep me going.
Perfect timing, I don't have to wait for this to be helpful. Thanks Prof Ben-Yaakov!
Thanks
Practical case about peak Vgs voltage holding if anyone is interested
Setup: IMBF170R1K0M1 SiC-FET (20 Vgs according to datasheet) acting as a switch, drived via the KSP2222 BJT in avalanche mode. No TVS or Zenner connected to g-s.
Mosfet holds a 120 Vp pulse on gate with 1.5 ns rise-time and 30 ns duration. Current pulse rise in the drain-load loop is about 2 ns. No gate breakdowns occured after many hours of working.
The duration of the applied pulse has a great importance. At more classical timing, like 1-10 uS pulse, gate breakdown occurs at 40-50 V already.
Is this backed up by the manufacturer?
@@sambenyaakov No, the manufacturer avoids mentioning such modes for commercial risks reasons.
As one engineer from Wolfspeed told me once - “We define values in the datasheets that we can guarantee based on data from our development and testing department. They are often underestimated, but still ensure a minimum number of failures. You can work above these limits - but this at your own risk, and we decline our liability in such cases."
I should probably warn those who read the previous message - if you are developing commercial electronics, do not go beyond the datasheet limits, otherwise you may incur serious costs. The case I described is purely laboratory-experimental, just to keep in mind. Good for IEEE/ResearchGate articles, but not for the market.
nice explanations. On 5:00 the RDS ON is assumed only dependent on temperature. this should be OK as long as the transistor is operated in saturation.
Indeed. Thanks for input.
Thanks prof. Sam .please note that on 13:35, the initial temperature is at the junction, and not at the case, as you said.
I don't follow. Which temp? Before the pulse, the temp of junction follows that of case.
The total energy the transistor dissipates is the inductor's stored energy PLUS the additional energy provided by the battery while the current is flowing. Given the two battery analogy, the left battery is charged while the right battery is discharged. The energy delivered by the battery is VIt/2... its voltage times the average current times the time to discharge the inductor.
This is correct but has been taken into account in the derivation. And if you missed this: no matter from where the current is coming, the energy absorbed by the transistor is always Q*Vbr.
Very good thank you sir.
Thanks
Hi sir when is your new video coming??
A bit overloaded. I hope in a few days😊Hold on, don't go anywehre
@@sambenyaakov sure sir ... without watching your video in weekend feels like boring so I was just making sure this weekend shouldn't go boring 😁
@@biswajit681 How can I resist such a nice request🙂 Highly appreciated. I promise an intersting weekend.
@@biswajit681 Have you seen this? Also intersting www.linkedin.com/posts/ben-yaakov-shmuel-sam-49094422_pop-quiz-what-is-this-circuit-extra-credit-activity-7184221013507772416-u5_u?
@@sambenyaakov yes sir ...this capacitance multiplier circuit I saw in old power supply design circuit pre filtering stages
👍🙏❤️
Thanks😊