Advanced temp/humidity Project 1/x - KiCad schematic
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- Опубликовано: 28 июн 2024
- Advanced temp/humidity schematic design - KiCad
Schematic design and electronics considerations for a touchscreen WiFi-enabled temperature and humidity board. It is based on an ESP32 and a 4DSystems touchscreen LCD display. The board also has a 5V to 3v3 buck converter. I focus on some more advanced circuit design techniques for ESD and EMC compliance.
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Only just stumbled over this channel. I really appreciate the fact that you are showing "overkill" design choices. There are plenty of tutorials and video showing the basics over and over, but very few take the time to show some more professional grade design choices. Thanks!
This was great! I'd love to see more like this. I'm looking forward to seeing the PCB layout process for this too.
Thanks! Yes, it is coming soon!
Instablaster
Nice to see any revisements and follow up on production of it
You bet!
Thanks for all your knowledge. I'm a newbie EE profesional working on product level power systems and what you're explaining is vital for passing compliance testing (UL) -- it separates the hobbiest from the pros.
Love these types of videos - I always learn something new from watching them. One thing I'd like to add is that you want to pay special attention to the TLP plots when selecting TVS diodes because the amperage flowing through them is a coefficient of the voltage they can clamp. Your diode might be rated for a 3V3 clamp but in an ESD scenario with a longer pulse that conducts more current, it may very well clamp ABOVE its rated maximum and your ICs could see 5, 6, or even higher voltage potentials. Also a suggestion: maybe setting up your connector vertically instead of horizontally to avoid having awkward connections and drawing through the symbol would make the schematic prettier?
Great point. I wish I would have mentioned that during the video - I'm considering doing a dedicated i/o pin protection video, covering ESD, over/under voltage, etc. I could cover it better there.
But yeah, you're right, but the key is that the vast majority of the power will be dumped by the TVS, and very little will be able to affect the ICs. Can it still destroy them? Of course, but the ICs themselves will always (we hope..) have ESD protection diodes built in, so as long as you handle most of the surge, they typically can take the rest. Adding some caps (with i2c you can't add much), series resistance (series R solves almost everything), or another TVS downstream all help to better your protection. With this circuit, I'm 99% confident that the screen will itself handle all ESD surges internally (We have a client with 100+ of them deployed with only caps as ESD protection, with 0 failures), so the lone TVS should be more than enough.
^ Definitely not trying to disagree, you're absolutely right, just throwing my reasoning out there :)
Don't know what I was thinking with the connector, definitely a total mess :p
@@MicroTypeEngineeringThat would be a good topic for a video, and I will definitely watch. I'm still trying to wrap my head around the various methods and combinations of overcurrent/overvoltage protection schemes. Also how do you guys calculate LC filter values? Is it just like a best guestimate type of thing(which is perfectly fine sometimes) or do you guys incorporate them with a specific range in mind or after observing particular interfering frequencies in prototypes? Thanks.
Check my response to @DavidEnds 12. Yeah it's a lot of guesswork/guestimates + actual baselines. Main thing is to filter out the first three harmonics of the highest frequency of the chip. If you use a lot of ceramics with low ESR, make sure to account for ringing.
Nice video. There were a lot of good nuggets of info here, such as chokes, and the whole 1 ohm resistor for the switching regulator.
Nano comes after micro. (When talking about decades of capacitance) Lots of super useful info, just had a minor panic attack when I thought I had made a mistake with all of my 100nF bypass caps.
These videos are gold! Thank you.
Excellent ! I learn way better on youtube, and after learning the basics your's video are really perfect for my level. Thaaaaaaannnkkkss
Nicely done. +1 for the test points. I tend to put them on things like the I2C lines, but that might be based more on pains of past projects than solid engineering. The TVS diodes on the lines coming back from the touchscreen are super obvious now that I see it, but that might have been a blind spot for me, had a used one in a project. On pluggable connectors, yes, obviously. But, what is the user going to touch more than anything? The screen. Face palm. Thanks. I have used PTC fuses in the past, in both the Zener + PTC and PTC-only configurations you showed in the video. So far, I haven’t seen magic smoke from the boards or powered devices. However, I’ve never felt confident designing with them. Simply put, my main hangups are the two current ratings and the time coefficient. Any chance you’d be willing to clear that up in the comments or in a future video? Either way, thanks for your efforts on the channel - it’s all good stuff.
Yeah. Honestly, as much as test points would be useful on lines that are used on boards, I virtually never use them. Throughout all my reworking/troubleshooting boards, if there's a pad, I can test it. So as long as there's a component on the net, I'm confident that I can get a probe on it. Yep, those TVS diodes are very good, cheap insurance. For the PTC fuses, I assume you mean the IH vs IT? Basically, make sure your device never goes above IH in normal operation. Between IH and IT it may be starting to open, maybe not. Above IT, depending on the time (as shown in the datasheet graph) it will open. Basically, for any fuse - standard or PTC - they are brute force, inaccurate devices. You really can't rely on them for an accurate trip. In this case, who cares at what current it trips at exactly? Will it trip on a dead short? Absolutely. That's my goal with fuses. Anything that needs accurate current protection needs an EFuse, or a true current limit circuit. (Though, I'll still have a fuse in series with those).
Might do a video on Li-ion protection circuits comining up. We're working on a UL design right now, so it's pretty fresh for me!
MicroType Engineering The one big plus of actual test points - even if they are just little solder pads - is that you can have multiple scope probes attached. Probing a single pin, even on a fine pitched part, isn’t too bad. But, they are more useful when you’re checking to see if X happens, then Y should follow. Anyway, I basically agree - I should probably reduce my reliance on them over time. Yes, exactly - IH vs IT. I really like the way you described/explained fuses in general, and it immediately changed my perspective. Looking back, I think I used these parts in exactly the way you described. But, at the time, doing so gave me a bad vibe, as it felt more like guesswork than thoughtful application. Now I see that, as your said, they’re an inherently crude instrument - and should be viewed & used as such. Thanks for taking the time to answer my question! It definitely helped.
Great stuff
excellent video. I learned a lot. I'm using the MicroType Engineering videos to raise my game. (I'm an amateur maker.)
Great to hear!
@@MicroTypeEngineering I submitted a schematic for you to critique. (at your webside submital URL).
nice am waiting part2 great
Great video, really liked the scope and pace. Good explanations, would like to hear some more details on buck reg and ferrite beads 👍
Noted!
You're the man!
awesome
I like this type of videos. Schematics and board layouts. You have shorted your choke in your schematic. Hope you noticed it before you sent it to PCB manufacturer ;)
Ha! Good catch. Nope, haven't done the PCB yet :D
I love your tutorials. I have learned a lot. Thanks.
I believe your schematic for the ESP32 auto flash/upload is wrong. According to Espressif documentation, Q2 emitter should be connected to DTR not IO0. In Espressif documentation, Q1 and Q2 symbols are drawn differently.
Nice video on the schematic design, learned a lot. Looking forward to the PCB design. Do you think you'll be able to do it on a 2 layer board?
That's the plan. Mostly finished with it, hoping to have it finished up soon.
I like this sort of video. As a noob, it brings in the LC stuff and also the choke my RUclips education (as you pointed out) has not easily given me. I was wondering how you choose the size of the inductor for the buck.. I assume it has to somehow work the the switching frequency and its counterpart cap along with amps out?
Correct. The higher the switching frequency, the smaller the inductor that is required. Most datasheet's will give you the calculation for it.
Can we see the final board and perhaps the assembly process of the board?
Yes! That's the plan
Can you release the fool pcb layout process of this
MOOREs the LAw!
I do not like the auto-programming circuit for ESP32, it is basically just a xor gate that protects you from resetting the MCU on opening the port on the PC, and it requires a capacitor on the EN pin for compatibility.
hello sie nice work how i can get your project or download
How do you calculate the capacitor Values?
Ahh now you will be going down the rabbit hole! Tldr; the smaller the capacitor, the better it is a shunting high frequencies. That's why I mentioned using one at each decade, as that is how the impedance vs frequency graphs make the most sense.
In reality, it's a lot of best guesses, rules of thumbs, and hoping for the best honestly. For the most part, you want to make sure to filter at least 3x the frequency of the highest switching speed on the board. (THIS IS BASED ON RISE TIME, NOT JUST OVERALL FREQUENCY!!!!) So, you can have a "slow" 16MHz chip, but it could have nano-second rise times, which are devastating to have on your board if you don't filter for them. Note: sometimes datasheets suck, and they don't show this spec, but... you do the best you can.
When you do this - filtering with a few decades of low esr caps - you need to make sure they don't "ring". That's why I have a larger electrolytic with a "R" in series. You can also just have a low value resistor in series with the power line to damp the ringing. Just be aware of this, as if you don't, you can make things so much worse than no filtering at all!
Check out:
TI appnote: SCAA048
Dave Jones has a fantastic video: ruclips.net/video/BcJ6UdDx1vg/видео.html
@@MicroTypeEngineering thanks!!!
Sorry, but I've got a bone to pick with this :). Splitting the value of capacitors in the same case size is BS that doesn't stand up to any scrutiny or measurement and annoys me every time I see people perpetrating it. Every time I've seen it, these are people blindly following "best practices" passed down to them without ever making measurements to check if what they're doing makes any sense or not. That 1000pF cap in parallel with the 10uF does _nothing_. It's time to break the chain of misinformation!
In a decoupling application, the impedance of the capacitor can be thought of in 3 different regions below resonance, at resonance and above resonance. Below resonance, the capacitive reactance dominates the impedance, so more capacitance leads to better decoupling. At resonance, the capacitive reactance is exactly canceled by the inductive reactance and all that remains is the ESR which is usually "low enough". Above resonance, the ESL dominates so less ESL leads to better decoupling. Now here's the kicker, the ESL is a function of the case size *not* the value of the capacitance. For the same case size, increasing the capacitance increases the self resonant frequency (SRF), but does *not* lower the the high frequency impedance. See this impedance plot: i.stack.imgur.com/BUUHk.png
The "capacitor from every decade" technique held water when the "bulk" capacitance was provided by a high ESL type, like an electrolytic. With modern MLCC's, to maximize decoupling is more about how you design the interconnects to the capacitor, since the external interconnect "ESL" will quickly swamp the internal ESL of the capacitor and dominate high frequency performance. Beyond that, it's about choosing the smallest size available, or using landscape, feedthrough or interdigitated termination capacitors (notice the theme of interconnects being the primary issue), but that is really only necessary for particularly high performance designs.
Hah! Glad you commented, always good to add to the discussion. Yup, hard to disagree with your reasoning. Though, the "curves" shown on the stack post are ideal, and not actually what a frequency vs impedance graph typically looks like. In reality, you get something more akin to this: n7f2x3w4.rocketcdn.me/wp-content/uploads/2017/04/SingCapImpdnce.gif (I know you're going to point out how the impedance differences decrease with smaller capacitance's. That's true, but there is still a difference) Smaller capacitance valued capacitors will tend to have a lower ESL (yes, package, land size, and traces make a much bigger difference).
ntuemc.tw/upload/file/20120419205619a4fcf.pdf Is a fantastic paper with real world testing of capacitors that goes into this topic in great detail. But yes, in reality, having capacitors of varying package sizes to minimize ESL is going to be the best approach. Using smaller capacitance values does also help, and to be able to achieve the smaller packages, typically the capacitance values are going to be decreased as well. So it isn't really an "either or" approach, you can do both.
The biggest issue with my approach and the standard "decade" system is the risk of self-resonance and ringing. That's why it's really important to make sure it is damped (series r, ferrite, something), and to keep from having large gaps in the ceramics capacitance values. That NTU paper shows a nice graph of this.
@@MicroTypeEngineering You're trying to make this more complicated than it is :). Those lines are *very* accurate to what actual performance is (I've done actual measurements to convince myself of this). I don't recognize the capacitor manufacturer for the plot you link, but it seems it's targeting *film* capacitors (which have a different case size for each value). You absolutely cannot draw conclusions from that plot for surface mount MLCC capacitors, and if you're counting on the little deviations in the high frequency performance of a parasitic parameter being "as advertised" in a +/-10 or 20% part well good luck!
For MLCC's the simpler answer is also the more accurate one: ESL is a constant with case size, so for best overall decoupling in a given case size pick the "biggest" value (that makes sense). If this doesn't give you adequate high frequency decoupling, dont go looking for lower values, look for smaller case sizes, (or better interconnects or exotic terminations). Murata publishes some of the best specs on this kind of thing, this link is a plot of several "decade" capacitors from the GRM series 0603 case size: ibb.co/rdyYsby Note that ESL is line-on-line for each of these caps, and the lowest value cap is lower impedance *nowhere*, except it's specific self-resonance. You can easily generate similar plots using the Simsurfing tool they provide for other MLCC families or case sizes.
I know you can find papers and app notes written in support of the strategy you take. All I can say, is "watch out!", EMI/EMC is an industry rife with cranks who stumble in the dark and do things based on intuition that they never actually submit to test. You don't need to take my word for it (and shouldn't) but I would recommend Henry Ott or Lee Hill or learnemc.com/ as generally authoritative sources. The paper you link for instance has multiple plots showing that MLCC's have the same ESL for a given case size, but gets the conclusion wrong on slide 47 that "ESL decreases with decreasing capacitance value", and "ESR is lower for higher capacitive values"
I don't think I'm making it more complicated? Again, I'm not disagreeing, I literally said above I can't disagree with you.. Maybe you're forgetting the simple fact that if you wanted to use an 0805/0603/0402/0201 to best obtain a low ESL curve, you physically would have to use different capacitor values, unless you wanted to use nF size for everything, which most likely won't be enough capacitance for the chip depending on what it is. So we're back to the decade solution... 0805/0603 at 1 or 0.1uF, 0402 10nF, 0201 1nF. You literally can't have all those packages at 0.1uF, as 0201 is too small for it.
@@MicroTypeEngineering To clarify, what I think is "overcomplicating" things is talking about picking multiple values for high frequency decoupling performance, when (admittedly counter-intuitively) the high frequency impedance has basically nothing to do with the capacitance value. When I've seen people do this "decade" stacking of capacitors before, I often do not see the case size modified for the smaller values. But maybe that was how you were planning to implement this?
I'm not promoting the solution is to have "one of each case size". At low frequency, everything other than the highest capacitance value is irrelevant, and at high frequency everything other than the lowest ESL (smallest case size) is irrelevant. My approach is to pick a decoupling capacitor that "makes sense" for the design, ie it's as small a package and as big a capacitance as I can get without driving my layout design rules or BOM cost, still has decent voltage rating and a decent dielectric, etc (also, you literally *can* get a 0.1uF 0201 ;) ). I then just use that everywhere, with a good low inductance footprint and anywhere I am extra concerned for whatever reason I stack multiples of that single value. If something needs a specific bulk capacitance somewhere, obviously I probably will use a different capacitor to achieve that.
Anyway, good luck with your design!