Hello Asaf, great observation. You are correct, the output across VDS will switch between 0 and Vout (actually Vout with the diode drop voltage). Because it is a boost converter Vout is larger than Vin. The average value across VDS s Vin, but for design you will need to use the max value for sizing. Please see the first part for the switching voltage waveforms ruclips.net/video/bTPjEsBd9mQ/видео.html. Thanks for watching. -Dr K
Awesome, video. Please, I would like to know whether the specified current and voltage ripples (5% and 1% respectively) base on IEEE Standard or you just used any random values?
Hi Benjamin, not these are not IEEE standards. Just assumptions that I made for the example. Every design will be different. If the voltage ripple is too small (say .05%), you will need a larger capacitor. The goal would be to have the largest possible ripple that meets the needs for the load voltage. Best wishes on your design and thanks for watching. -Dr. K
Thanks for your response. Please, I would like to know if you could share your email with me so that I could reach out to you for some clarification on my project. Thanks
Awesome video, there is one thing that I do not understand. Why sometimes output capacitor sizing equation have some constant, for instance, in your buck boost design video, there is a factor of 1/8 for the capacitor equation. I'm some data sheets, I've seen a factor of 9 for output capacitor in boost converters. How do we arrive to that result? How much the ic influences in this equation? Personally I'm using the MC33063 from TI as an inverting buck boost converter (IBB) and the output capacitor equation for both IBB and boost, has a factor of 9 which increases a lot the value of the capacitor for relatively normal output voltage ripples (50-100mV). Thanks for your help!
Hi Matias, The equation for the output capacitor is based on the amount of voltage ripple you will allow at full load and then depends on the type of converter you are using, as you noticed. For the buck converter, the capacitor has to sink and source charge and does so every 1/2 switching period. The amount of charge sourced to the load is 1/2(delta Io/2)*Ts/2 or (1/8)*(delta_Io/fs). The cap only sources charge when the current from the pass inductor sags below Io. The buck-boost topology is not straightforward. See the following for more information ruclips.net/video/va5uEOtGdU8/видео.html. Also, I'm not sure why the TI datasheet had a factor of 9. It could be that the equation is taking into account the range of duty cycle values or is a good empirical number. If you find more details, please let me know. Best wishes on your design. -Dr .K
Dear professor, I would like to simulate the circuit in real time for measurements in different nodes or modifying parameters and look how the circuit reacts in real time, which software do you recommend that stands circuits with feedback without software crashes (convergence error like in multisim) in the simulation. Thanks in advance.
Hi Jenish, my dashboard shows 38 "likes" and "0" dislikes as of today. Lol...Hope you found Part 2 useful. Most people just watch Part 1. Best wishes on your design.
Hello Priyanka, the equation for the gain of the Boost Converter is developed in Part 1 of this series. Here's the link ruclips.net/video/bTPjEsBd9mQ/видео.html
![[Limbus Company - PV] Chapter.7 - Oblivion](http://i.ytimg.com/vi/VUpkXPkvoxU/mqdefault.jpg)
Absolute treasure of a video!
Thank you.
Great explanation. A question - why the VDS should be larger than Vin and not Vout? The transistor voltage changes between ~0V to Vout.
Hello Asaf, great observation. You are correct, the output across VDS will switch between 0 and Vout (actually Vout with the diode drop voltage). Because it is a boost converter Vout is larger than Vin. The average value across VDS s Vin, but for design you will need to use the max value for sizing. Please see the first part for the switching voltage waveforms ruclips.net/video/bTPjEsBd9mQ/видео.html. Thanks for watching. -Dr K
@@powerelectronicswithdr.k1017 Thanks for the answer. I saw the first part. Your explanations are great!
Awesome, video. Please, I would like to know whether the specified current and voltage ripples (5% and 1% respectively) base on IEEE Standard or you just used any random values?
Hi Benjamin, not these are not IEEE standards. Just assumptions that I made for the example. Every design will be different. If the voltage ripple is too small (say .05%), you will need a larger capacitor. The goal would be to have the largest possible ripple that meets the needs for the load voltage. Best wishes on your design and thanks for watching. -Dr. K
Thanks for your response. Please, I would like to know if you could share your email with me so that I could reach out to you for some clarification on my project. Thanks
@@benjamingomado5064 Hi Benjamin, you can find me in the Milwaukee School of Engineering faculty directory.
Awesome video, there is one thing that I do not understand. Why sometimes output capacitor sizing equation have some constant, for instance, in your buck boost design video, there is a factor of 1/8 for the capacitor equation. I'm some data sheets, I've seen a factor of 9 for output capacitor in boost converters. How do we arrive to that result? How much the ic influences in this equation?
Personally I'm using the MC33063 from TI as an inverting buck boost converter (IBB)
and the output capacitor equation for both IBB and boost, has a factor of 9 which increases a lot the value of the capacitor for relatively normal output voltage ripples (50-100mV).
Thanks for your help!
Hi Matias,
The equation for the output capacitor is based on the amount of voltage ripple you will allow at full load and then depends on the type of converter you are using, as you noticed. For the buck converter, the capacitor has to sink and source charge and does so every 1/2 switching period. The amount of charge sourced to the load is 1/2(delta Io/2)*Ts/2 or (1/8)*(delta_Io/fs). The cap only sources charge when the current from the pass inductor sags below Io. The buck-boost topology is not straightforward. See the following for more information ruclips.net/video/va5uEOtGdU8/видео.html. Also, I'm not sure why the TI datasheet had a factor of 9. It could be that the equation is taking into account the range of duty cycle values or is a good empirical number. If you find more details, please let me know. Best wishes on your design. -Dr .K
Dear professor, I would like to simulate the circuit in real time for measurements in different nodes or modifying parameters and look how the circuit reacts in real time, which software do you recommend that stands circuits with feedback without software crashes (convergence error like in multisim) in the simulation. Thanks in advance.
2.5k views and zero dislikes. Nice.
Hi Jenish, my dashboard shows 38 "likes" and "0" dislikes as of today. Lol...Hope you found Part 2 useful. Most people just watch Part 1. Best wishes on your design.
@@powerelectronicswithdr.k1017 Sorry, I meant 0 dislikes. Thank you sir for the reply. I was not at all expecting it.
How to calculate gain function M(D)
Hello Priyanka, the equation for the gain of the Boost Converter is developed in Part 1 of this series. Here's the link ruclips.net/video/bTPjEsBd9mQ/видео.html