Common LVS Errors and How to Fix Them - ECE x321 EDA Tutorial 5
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- Опубликовано: 11 дек 2022
- In this video, we will look at an almost complete layout to try and fix any remaining errors. We will use the LVS report to track down errors, as well as the extracted and schematic views to help us identify where errors might be.
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thank you for uploading this video!! I started using cadence not long ago in college and this was the first time that I had to use LVS, I was going crazy trying to fix my errors, but it got a lot easier thanks to you!!
Glad it was helpful! What's even more unfortunate is that each design kit will have slightly different outputs on LVS, so your experience may differ if you are using a different kit (IBM vs TSMC, for example). Thankfully, if you're familiar with one type of LVS, you can usually figure out quickly where the errors are!
this just saved my life! thank you so much i was about to start all over again but i finally got it thanks to you!!
Glad I could help! Cadence isn't exactly an easy software to learn, but learning how to fix LVS errors makes your job a lot easier.
How to solve "property error" in LVS?
In the very beginning you have shown the si.out @2:10secs that, Layout has 11 nets and schematic have 8 nets. And then you mentioned that "there are few connections missing in the layout". My questions are:
1. How can Layout have more nets than Schematic?
2. If layout has more number of nets than schematic how can you say that "there are few nets missing in Layout", but not missing in schematic. (I know schematic can't be wrong, but how can you say, the one with more number (Layout) of nets has missing connections but not the one with less number of nets (schematic) )
Great questions, I'll address each one individually.
1. The layout can very easily have more nets than the schematic if we aren't careful. Let's consider a simple case where one transistor drain (D1) connects to another transistor source (S2). In our schematic, since we should have D1 and S2 connected, they will form one "net." In the layout, however, if we don't connect D1 and S2, then we will instead have two "nets": one that includes D1 and another that includes S2. So if we are missing a connection, then the number of layout nets will increase. Conversely, if we accidentally connect two wires that should not be connected, the number of layout nets will decrease. You can use this to get an idea of what kind of errors you are searching for.
2. We generally assume that the schematic is correct, since we can perform simulation on it very easily. If we are making an amplifier, we can simulate the loop gain and time-domain performance to make sure it works well. From here, we can then try to match our layout with our schematic that we know works. If you don't simulate the schematic to verify that it works, then you have no way of knowing if the layout you are making is actually correct.
Hope this helps!
I Understood the 1st answer, but the 2nd question still stays, " there are few nets missing in Layout ". I mean, if you say, there are few "connections" missing, I understand. Because as you mentioned in your 1st answer that, we may get two nets - 1 for D1 and another for S2, which means they are not connected.
But you said "nets" are missing. How can we come to that conclusion is what I am unable to deduce.
Thanks a lot of the help.
How to solve the missing instance error?
If you have a missing instance error, it is likely that a transistor or passive component is missing from your schematic/layout, depending on the specifics of the error. You will likely need to find the specific instance that does not match to discover the origin of the error.