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- Просмотров 639 178
Electronics Insight
Индия
Добавлен 23 апр 2020
Mealy State Machine: Overlapping Sequence Detector
This video illustrates the basics of Finite State Machine (FSM), types (Mealy & Moore Model), and its detection techniques (Overlapping & Non-overlapping sequence). Then, the video concentrates specifically on the overlapping sequence detection of 1011 and 101. The complete design steps are discussed for Mealy overlapping sequence detector.
Просмотров: 2 417
Видео
Signed Multiplication - Booth's Algorithm
Просмотров 2,4 тыс.2 года назад
The video helps you to perform multiplication of signed binary numbers using Booth's Algorithm.
PN Diode: Junction Capacitance, Current & Storage Capacitance - Solved Problem #shorts
Просмотров 3192 года назад
This is a short video which helps you to solve problems on PN Junction Diode current and capacitance. Junction capacitance - dominant at reverse bias also known as Depletion / Transition capacitance. Storage capacitance - due to forward bias is also known as Diffusion capacitance. #shorts
PN Diode - Junction / Depletion / Transition Capacitance - Solved Problem #shorts
Просмотров 2592 года назад
This is a short video which helps you to solve problems related to PN Diode - Junction Capacitance, also known as Depletion or Transition capacitance. It is dominant under reverse bias.
PN Junction Diode - Built-in Potential, Depletion Width, Electric Field & Charge: Solved Problem
Просмотров 4502 года назад
This is a short video on solved problem related to PN Junction Diode. #shorts
Generation & Recombination Process - Excess Carrier Concentration
Просмотров 6542 года назад
This video helps you to understand about the generation and recombination process and helps to solve problems related to Excess Carrier Concentration. Carrier concentration - Compensation - Charge Neutrality -Mass Action Law - Part I ruclips.net/video/x89aZw0-0m0/видео.html Carrier concentration - Compensation - Charge Neutrality -Mass Action Law - Part II - Solved Problem ruclips.net/video/wuw...
Carrier Concentration (Intrinsic, Electron & Hole) - Fermi Level - Density of States (DoS)
Просмотров 3672 года назад
This video helps you to solve problems related to Carrier Concentration (Intrinsic, Electron & Hole) - Fermi Level - Density of States (DoS). Carrier concentration - Compensation - Charge Neutrality -Mass Action Law - Part I ruclips.net/video/x89aZw0-0m0/видео.html Carrier concentration - Compensation - Charge Neutrality -Mass Action Law - Part II - Solved Problem ruclips.net/video/wuwEMWh-k14/...
Carrier concentration - Compensation - Charge Neutrality -Mass Action Law - Part II - Solved Problem
Просмотров 3352 года назад
This video helps you to solve problems related to carrier concentration (Hole & Electron), compensation doping, and charge neutrality. The first part of the video link is shared below, which is a review of all these concepts: ruclips.net/video/x89aZw0-0m0/видео.html
Semiconductor: Carrier concentration - Compensation - Charge Neutrality -Mass Action Law - Part I
Просмотров 5212 года назад
This video is a review of semiconductor types, carrier concentration (Hole & Electron), compensation doping, and charge neutrality. Energy Bands in Semiconductor: ruclips.net/video/xy3K5FI2xUY/видео.html
The Ebers Moll Model of N-P-N Transistor - Large Signal Model of BJT
Просмотров 4,5 тыс.2 года назад
This video helps in understanding the PN Junction Diode to BJT analogy. Also, a brief review on PN Junction diode currents are also described. The large signal model / Ebers Moll model of N-P-N transistor to determine the dc terminal (Base, Collector & Emitter) currents in four different modes of operation namely, cut-off, saturation, forward active and reverse active mode.
NPN - Common Emitter Connection | Cut-Off & Saturation Points| Theory & Solved Problem
Просмотров 4843 года назад
This video helps you to determine the state of a transistor in a Common Emitter (CE) connection. Active, Cut-off & saturation state of the transistor is discussed with two different types of solved problem. Bipolar Junction Transistor | Common Base Connection | Theory & Solved Problem ruclips.net/video/bczgz7vfHWI/видео.html Bipolar Junction Transistor | Common Emitter Connection | Theory & Sol...
NPN - Common Emitter Connection | Load Line Analysis | Operating Point | Theory & Solved Problem
Просмотров 4193 года назад
This video helps you to understand the d.c. load line analysis in a Common Emitter (CE) connection of NPN transistor. Also, the output characteristics of CE connection is discussed along with load line analysis with a solved problem to determine the Q-points of transistor. Bipolar Junction Transistor | Common Base Connection | Theory & Solved Problem ruclips.net/video/bczgz7vfHWI/видео.html Bip...
Bipolar Junction Transistor | Common Emitter Connection | Theory & Solved Problem
Просмотров 3583 года назад
This video helps you to understand the Common Emitter (CE) connection of NPN transistor. Also, the steps to derive base current amplification factor and total collector current has been explained with a solved problem. The relationship between current gains of CB and CE connections has been explained. Bipolar Junction Transistor | Common Base Connection | Theory & Solved Problem ruclips.net/vid...
Bipolar Junction Transistor | Common Base Connection | Theory & Solved Problem
Просмотров 5943 года назад
This video helps you to understand about BJT, different types of BJT and its symbols. Also, Common Base (CB) connection has been explained to derive current amplification factor and total collector current with a solved problem.
Special Diode Circuits | Zener Diode (Fixed Vi and RL) | Solved Problem
Просмотров 1,1 тыс.3 года назад
This video helps you to solve problem related to Zener Diode. The solution is clearly explained to extract the unknown parameters in the Zener Diode network.
Special Diode Circuits | Zener Diode | Load & Line Regulation | Solved Problems
Просмотров 7473 года назад
Special Diode Circuits | Zener Diode | Load & Line Regulation | Solved Problems
Full wave Rectifier | Centre Tapped Rectifier| Solved Problem
Просмотров 8673 года назад
Full wave Rectifier | Centre Tapped Rectifier| Solved Problem
Full wave - Centre Tapped & Bridge Rectifier| Theory | Efficiency, Ripple Factor Derivation
Просмотров 3493 года назад
Full wave - Centre Tapped & Bridge Rectifier| Theory | Efficiency, Ripple Factor Derivation
Diode Circuits | Half-wave Rectifier | Solved Problem
Просмотров 5743 года назад
Diode Circuits | Half-wave Rectifier | Solved Problem
Diode Circuits | Half-wave Rectifier | Theory | Efficiency, Ripple Factor Derivation
Просмотров 3383 года назад
Diode Circuits | Half-wave Rectifier | Theory | Efficiency, Ripple Factor Derivation
Series & Parallel Circuits | Equivalent values of R, L, C | Solved Problems
Просмотров 3773 года назад
Series & Parallel Circuits | Equivalent values of R, L, C | Solved Problems
Serial & Parallel Circuits | Using Current & Voltage Division Rule
Просмотров 7403 года назад
Serial & Parallel Circuits | Using Current & Voltage Division Rule
GATE 2015 - ECE | Solved Problem on NMOS Transistor with Active Load | I-V Characteristics
Просмотров 6563 года назад
GATE 2015 - ECE | Solved Problem on NMOS Transistor with Active Load | I-V Characteristics
Current Division Rule in Parallel circuits - TinkerCAD online simulation tool
Просмотров 7783 года назад
Current Division Rule in Parallel circuits - TinkerCAD online simulation tool
GATE 2021 - ECE | Solved Problem on Long Channel MOS Transistor | I-V Characteristics
Просмотров 7363 года назад
GATE 2021 - ECE | Solved Problem on Long Channel MOS Transistor | I-V Characteristics
GATE 2016 - ECE | Solved Problem on Long Channel MOS Transistor | I-V Characteristics
Просмотров 6243 года назад
GATE 2016 - ECE | Solved Problem on Long Channel MOS Transistor | I-V Characteristics
GATE 2014 - ECE | Solved Problem on NMOS Transistor with Resistive Load | I-V Characteristics
Просмотров 7923 года назад
GATE 2014 - ECE | Solved Problem on NMOS Transistor with Resistive Load | I-V Characteristics
GATE 2014 - ECE | Solved Problem on Channel Length Modulation (CLM) Effect
Просмотров 1,5 тыс.3 года назад
GATE 2014 - ECE | Solved Problem on Channel Length Modulation (CLM) Effect
NMOS Inverter with Resistive Load - LTSpice Modeling & Simulation
Просмотров 3,7 тыс.3 года назад
NMOS Inverter with Resistive Load - LTSpice Modeling & Simulation
Channel Length Modulation (CLM) | Punch Through Effect | Non - ideal Effects of MOS Transistor
Просмотров 3,5 тыс.3 года назад
Channel Length Modulation (CLM) | Punch Through Effect | Non - ideal Effects of MOS Transistor
Thank you So much mam !
Thank you So much mam !
Thank you so much mam !
Thank you mam for such a wonderful video !
Thank you mam !
you are life saver !
mam tmr is my FAT exam and ur videos are a live safer THANKQQ
Good
You saved my life mam really great lecture in simple and crisp manner it helped in my master exams
Great explanation 👏👏
Mam can you please upload videos for DSD?
best explanation with suitable examples
So helpful❤
You made this concept so easy. Thank you
Mam thanks for your video Tommorrow is my EMD exam it is very useful for me
what to do if VDD and VSS are not given in layout diagram
Please start some course in PDK flow (DRC , LVS, PEX) also.
The one and only clear tutorial on drawing a state diagram for any sequence detector
Thank you soo much for the detailed explanation
i did not understand the point of inverters in D-LATCH(transmission gate) what happens if we dont put them means will our circuit give wrong output
in simulation part you have not increased w\l of pmos for beta=1 to compensate for low mobility of pmos just this part is unclear
VERY nice effort by mam. She stays focused on teaching while her roomie plays random jingles😤
if u interchange the source and drain in your question which normally should be as current in nmos is conventionally from drain to source we get the same voltage at given nodes i guess
I have one doubt If you don't know output voltagw so how can you assume it 5v then 2.5v then 0v ...
Thank you for the shortcut and the detailed explanation!
In 4th case how did Vout=5 in PMOS case Vdsp=Vout-Vdd= 1-5=-4
thank you so much!! i wouldn't be able to understand this subject without this video.
mam please make for a negetive edge trigered register using transmission gate please do it mam as soon a possible
i love the diagram. it is so helpful for me to understand the explanation. thank you!
you are a very smart mam I can feel it by your explainnation thanks a lot making this series
mam your voce is so sweet as well as teaching quality.....take love from Bangladesh.
great
crystal clear mam THANK YOU
Thanks mam
I hope you can have more clear videos
very good explanation. Better than Purdue University professor
Can you please upload the static cmos representation of layout diagram
Missed the topic in class, thank you for explaining this in detail !
Love your explanation thankyou mam I see a lot of channels for this content no one explain like this 😊
I wish i had u in vellore vit for my course
best future try to make more videos
Very clear explanation
One of the best and smoothes explained throughout youtube
Nice explaination mam
#voltaic ingenious legenda
Thank you so much. You have helped me a lot.❤❤
thank uuu so much
Thanks for the explained video, couldn't find any better video
It's very clear to understand ❤
Thank you maam you are Life saver.