FPGA Discovery (Learning How to Work with FPGAs)
FPGA Discovery (Learning How to Work with FPGAs)
  • Видео 67
  • Просмотров 134 175
CPU Series 1: The 7-Step Processor Part 6 - CPU Verification and Programming
In this video, the functionality and correctness of design of the CPU is verified through a testing process that includes writing programs for the CPU, assembling CPU programs into binary machine codes, creating a Verilog ROM containing the machine codes, transferring machine codes to CPU memory, and driving the CPU to execute the coded instructions.
Special thanks to Wenton Davis for supporting this project by writing the assembler.
Video Corrections:
3:55 - Not "semicolon", but "colon", to mark a label in an assembly program. The semicolon in an assembly program is used for comments.
11:48 - Double click on the "Python program file", not the "ROM".
18:12 - Not back to "step 6", but back to "...
Просмотров: 550

Видео

CPU Series 1: The 7-Step Processor Part 5 - A Complete CPU22:59CPU Series 1: The 7-Step Processor Part 5 - A Complete CPU
CPU Series 1: The 7-Step Processor Part 5 - A Complete CPU
Просмотров 295Год назад
In this video, a new data bus design is introduced, the remaining small CPU components are created along with a couple new components. Each component is simulated to verify functionality. Finally, the complete CPU is created in one Verilog module and a preview of Part 6 discusses a plan for verifying the operation of the completed CPU. Github space containing CPU_B: github.com/FPGADude/Digital-...
Improved Nexys A7 I2C Temperature Sensor5:55Improved Nexys A7 I2C Temperature Sensor
Improved Nexys A7 I2C Temperature Sensor
Просмотров 1,1 тыс.Год назад
An improved version of the previous Nexys A7 Temperature Sensor project. Improvements: reset removed (not needed), single always block in i2c master, and added Fahrenheit temperature conversion circuitry and display capabilities. Project files located here: github.com/FPGADude/Digital-Design/tree/main/FPGA Projects/Improved I2C Nexys A7 Temperature Sensor
I2C on FPGA Temperature Sensor Basys3 with PmodTMP26:59I2C on FPGA Temperature Sensor Basys3 with PmodTMP2
I2C on FPGA Temperature Sensor Basys3 with PmodTMP2
Просмотров 3 тыс.Год назад
Using the PmodTMP2 requires modeling the PMOD pins on the FPGA with pullup resistors. The same files from Nexys A7 can then be used with PmodTMP2. This project adds functionality to switch between outputting Celsius and Fahrenheit temperature data. Project files located here: github.com/FPGADude/Digital-Design/tree/main/FPGA Projects/Basys3_PmodTMP2_Temp_Sensor
CPU Series 1: The 7-Step Processor Part 4 - Control Unit and Instruction Set1:03:34CPU Series 1: The 7-Step Processor Part 4 - Control Unit and Instruction Set
CPU Series 1: The 7-Step Processor Part 4 - Control Unit and Instruction Set
Просмотров 325Год назад
This video covers the control unit schematic and the processor instruction set. This is a long video, but the information within is paramount to understanding how the processor works and how it can be utilized within a computer system. Icarus Verilog download: bleyer.org/icarus/ Project files GitHub repository location: github.com/FPGADude/Digital-Design/tree/main/Microprocessor CPU Series/7 St...
CPU Series 1: The 7-Step Processor Part 3 - Clocks and Stepper9:00CPU Series 1: The 7-Step Processor Part 3 - Clocks and Stepper
CPU Series 1: The 7-Step Processor Part 3 - Clocks and Stepper
Просмотров 333Год назад
In this part we begin to examine the control unit in which the clock generation and stepper modules reside. We build the clock generation and stepper unit, and then test both using a Verilog test bench using Icarus Verilog and GTKWave. At the end of the video is a preview of the control unit that will be built using Verilog in Part 4. Link to Icarus Verilog and GTKWave: bleyer.org/icarus/ Link ...
CPU Series 1: The 7-Step Processor Part 2 - Arithmetic and Logic Unit (ALU)16:15CPU Series 1: The 7-Step Processor Part 2 - Arithmetic and Logic Unit (ALU)
CPU Series 1: The 7-Step Processor Part 2 - Arithmetic and Logic Unit (ALU)
Просмотров 267Год назад
Part 2 of the 7 Step Processor series. In this video we build the ALU from the logic schematic provided in the book. Then test it using a test bench module to verify its operation. Video corrections: 12:37 - operand B is "hex 55" not "hex CC" Link to Icarus Verilog and GTKWave: bleyer.org/icarus/ Link to Github repo with project files: github.com/FPGADude/Digital-D...
CPU Series 1: The 7-Step Processor Part 1 - Main Memory (RAM)19:55CPU Series 1: The 7-Step Processor Part 1 - Main Memory (RAM)
CPU Series 1: The 7-Step Processor Part 1 - Main Memory (RAM)
Просмотров 666Год назад
The first video in a series where we will build a simple microprocessor described in the book "But How Do It Know" by J. Clark Scott. Disclaimer: I do not personally know the author of the book, nor am I promoting this book. It is just a really cool book filled with logic schematics describing a simple 7-step microprocessor that I thought would be fun to build and test using Verilog. Video corr...
UART in Verilog on Basys3 FPGA using PuTTY15:24UART in Verilog on Basys3 FPGA using PuTTY
UART in Verilog on Basys3 FPGA using PuTTY
Просмотров 8 тыс.Год назад
Using a UART core coded in Verilog and PuTTY terminal emulator to communicate ASCII values between a PC and an FPGA. Download PuTTY here: putty.org Project files located here: github.com/FPGADude/Digital-Design/tree/main/FPGA Projects/UART
FIFO in Verilog on Basys3 FPGA14:54FIFO in Verilog on Basys3 FPGA
FIFO in Verilog on Basys3 FPGA
Просмотров 1,5 тыс.2 года назад
Creating a 3-bit data, 4-address memory FIFO in Verilog and demonstrating functionality on the Basys 3 FPGA using Vivado. Project code can be found here: github.com/FPGADude/Digital-Design/tree/main/FPGA Projects/FIFO
SPI on FPGA 3-Axis Accelerometer Nexys A7 or Basys 3 w/ PmodACL2 Verilog32:29SPI on FPGA 3-Axis Accelerometer Nexys A7 or Basys 3 w/ PmodACL2 Verilog
SPI on FPGA 3-Axis Accelerometer Nexys A7 or Basys 3 w/ PmodACL2 Verilog
Просмотров 4,1 тыс.2 года назад
Reading the 3-axis accelerometer ADXL362 on the Nexys A7 using SPI serial communications protocol in Verilog using Vivado. You can also use the Basys 3 FPGA with Pmod ACL2 which has the ADXL362. Website for Icarus Verilog: iverilog.icarus.com/ Project files located here: github.com/FPGADude/Digital-Design/tree/main/FPGA Projects/Nexys A7 3-Axis Accelerometer SPI
I2C on FPGA Temperature Sensor Nexys A7 or Basys 3 w/ Pmod TMP2 Verilog41:27I2C on FPGA Temperature Sensor Nexys A7 or Basys 3 w/ Pmod TMP2 Verilog
I2C on FPGA Temperature Sensor Nexys A7 or Basys 3 w/ Pmod TMP2 Verilog
Просмотров 10 тыс.2 года назад
Reading the temperature sensor ADT7420 on the Nexys A7 FPGA with I2C master created using Verilog and implemented on FPGA with Xilinx Vivado. Can also use the Basys 3 FPGA with Pmod TMP2 which has the ADT7420. Website for Icarus Verilog: bleyer.org/icarus/ Project files on Github here: github.com/FPGADude/Digital-Design/tree/main/FPGA Projects/NexysA7_Temp_Sensor_I2C
Counters in Logisim2:38Counters in Logisim
Counters in Logisim
Просмотров 3152 года назад
Demonstrating four different 4-bit counters in Logisim Evolution. Binary Counter Johnson Counter LFSR, xnor version LFSR, xor version
Linear Feedback Shift Register LFSR in Verilog on Basys 3 FPGA5:25Linear Feedback Shift Register LFSR in Verilog on Basys 3 FPGA
Linear Feedback Shift Register LFSR in Verilog on Basys 3 FPGA
Просмотров 9882 года назад
Demonstrating a 4-bit LFSR on Basys 3 FPGA coded in Verilog. Project files can be found here: github.com/FPGADude/Digital-Design/tree/main/FPGA Projects/LFSR 4-bit
Johnson Counter in Verilog on Basys 3 FPGA4:34Johnson Counter in Verilog on Basys 3 FPGA
Johnson Counter in Verilog on Basys 3 FPGA
Просмотров 3972 года назад
Demonstrating a Johnson Counter on the Basys 3 FPGA using Verilog. Program files can be found here: github.com/FPGADude/Digital-Design/tree/main/FPGA Projects/Johnson Counter 4-bit
Fibonacci Sequence Generator Circuit in Logisim Evolution4:02Fibonacci Sequence Generator Circuit in Logisim Evolution
Fibonacci Sequence Generator Circuit in Logisim Evolution
Просмотров 1,3 тыс.2 года назад
Fibonacci Sequence Generator Circuit in Logisim Evolution
Star Wars Imperial March Song on Basys 3 Verilog Vivado10:32Star Wars Imperial March Song on Basys 3 Verilog Vivado
Star Wars Imperial March Song on Basys 3 Verilog Vivado
Просмотров 1 тыс.2 года назад
Star Wars Imperial March Song on Basys 3 Verilog Vivado
PicoBlaze Sum of Squares on Nexys A7 FPGA Verilog Vivado12:16PicoBlaze Sum of Squares on Nexys A7 FPGA Verilog Vivado
PicoBlaze Sum of Squares on Nexys A7 FPGA Verilog Vivado
Просмотров 2432 года назад
PicoBlaze Sum of Squares on Nexys A7 FPGA Verilog Vivado
Intro to PicoBlaze Microcontroller on Basys 3 FPGA9:55Intro to PicoBlaze Microcontroller on Basys 3 FPGA
Intro to PicoBlaze Microcontroller on Basys 3 FPGA
Просмотров 1,1 тыс.2 года назад
Intro to PicoBlaze Microcontroller on Basys 3 FPGA
Simple Register File in Verilog Simulated in Vivado6:39Simple Register File in Verilog Simulated in Vivado
Simple Register File in Verilog Simulated in Vivado
Просмотров 1,5 тыс.2 года назад
Simple Register File in Verilog Simulated in Vivado
Compare Basys 3 to Nexys A7 & Stopwatch/Timer on Nexys A7 Verilog Vivado10:52Compare Basys 3 to Nexys A7 & Stopwatch/Timer on Nexys A7 Verilog Vivado
Compare Basys 3 to Nexys A7 & Stopwatch/Timer on Nexys A7 Verilog Vivado
Просмотров 7072 года назад
Compare Basys 3 to Nexys A7 & Stopwatch/Timer on Nexys A7 Verilog Vivado
VGA Clock & Calendar Verilog Basys 3 FPGA18:23VGA Clock & Calendar Verilog Basys 3 FPGA
VGA Clock & Calendar Verilog Basys 3 FPGA
Просмотров 1,4 тыс.2 года назад
VGA Clock & Calendar Verilog Basys 3 FPGA
A Simple ALU in Verilog Simulated in Vivado7:50A Simple ALU in Verilog Simulated in Vivado
A Simple ALU in Verilog Simulated in Vivado
Просмотров 1,7 тыс.2 года назад
A Simple ALU in Verilog Simulated in Vivado
Driving RGBs with PWM on Cora Z7-10 FPGA Verilog Vivado3:42Driving RGBs with PWM on Cora Z7-10 FPGA Verilog Vivado
Driving RGBs with PWM on Cora Z7-10 FPGA Verilog Vivado
Просмотров 4662 года назад
Driving RGBs with PWM on Cora Z7-10 FPGA Verilog Vivado
VGA Digital Clock in Verilog on Basys 3 FPGA Vivado17:07VGA Digital Clock in Verilog on Basys 3 FPGA Vivado
VGA Digital Clock in Verilog on Basys 3 FPGA Vivado
Просмотров 3,1 тыс.2 года назад
VGA Digital Clock in Verilog on Basys 3 FPGA Vivado
VGA Project Pong pt3 Complete Game with NES Controller Verilog Basys 3 FPGA Vivado4:30VGA Project Pong pt3 Complete Game with NES Controller Verilog Basys 3 FPGA Vivado
VGA Project Pong pt3 Complete Game with NES Controller Verilog Basys 3 FPGA Vivado
Просмотров 1,5 тыс.2 года назад
VGA Project Pong pt3 Complete Game with NES Controller Verilog Basys 3 FPGA Vivado
VGA Project Pong pt2 Complete Game Verilog Basys 3 FPGA Xilinx Vivado20:27VGA Project Pong pt2 Complete Game Verilog Basys 3 FPGA Xilinx Vivado
VGA Project Pong pt2 Complete Game Verilog Basys 3 FPGA Xilinx Vivado
Просмотров 4,7 тыс.2 года назад
VGA Project Pong pt2 Complete Game Verilog Basys 3 FPGA Xilinx Vivado
VGA PmodENC Project Verilog Basys 3 FPGA Vivado7:04VGA PmodENC Project Verilog Basys 3 FPGA Vivado
VGA PmodENC Project Verilog Basys 3 FPGA Vivado
Просмотров 5082 года назад
VGA PmodENC Project Verilog Basys 3 FPGA Vivado
How to use PmodENC Rotary Encoder on FPGA, Basys 3 Verilog Vivado6:44How to use PmodENC Rotary Encoder on FPGA, Basys 3 Verilog Vivado
How to use PmodENC Rotary Encoder on FPGA, Basys 3 Verilog Vivado
Просмотров 8942 года назад
How to use PmodENC Rotary Encoder on FPGA, Basys 3 Verilog Vivado
Making the Basys 3 FPGA Portable Verilog Vivado3:37Making the Basys 3 FPGA Portable Verilog Vivado
Making the Basys 3 FPGA Portable Verilog Vivado
Просмотров 1082 года назад
Making the Basys 3 FPGA Portable Verilog Vivado

Комментарии

  • @aleenamajeed6695
    @aleenamajeed6695 8 часов назад

    Hi! I am trying to implement this code on a different FPGA board but am still using the same temp sensor. The board I am using is the Urbana board, and for some reason when I program the FPGA on Vivado, the only thing I read on the LEDs is 23 F and 0 C, and this is wrong for my room temperature which is 74 F, and this number doesn't change even when I apply heat to it directly. Does anyone have any advice or an idea on what the issue could be and a potential solution? Thanks so much!

  • @0323craft
    @0323craft День назад

    Sir how can I do mapping for output variable "cols"? Should I type xdc file manually? I think I was be able to do mapping only for input variables. Thank you for your kind explanation.

    • @dajoma36
      @dajoma36 21 час назад

      Hi. I'm assuming that you want to output cols. What do you want to output to, LEDs? Yes, you would need to manually update the XDC file for the outputs.

    • @0323craft
      @0323craft 10 часов назад

      @@dajoma36 Thank you for your kind explanation. Actually, I do not output cols directly to LEDs. What I have to do is to transform keypad signal into a 3-bit Opcode of ALU e.g. 0 into addition signal, 1 into subtraction signal. Thus, I have to put keypad signal into 7-bit variable and, using MUX, make the 7-bit value into 3-bit Opcode.

    • @0323craft
      @0323craft 9 часов назад

      I thought row and col signal should be input of my ALU so that I can use the 7-bit signal from keypad as a Opcode, but somehow I failed. Your video showed me that "col" signal shoud be handled as "output variable, manually mapped in xdc file". I would be very grateful if you let me know I understand properly. Thank you for reading my comment in spite of my bad english, sir. :)

  • @chasenoorda9931
    @chasenoorda9931 7 дней назад

    Great video

  • @chasenoorda9931
    @chasenoorda9931 7 дней назад

    The z direction could be always in the positive direction because it’s always sensing gravity.

  • @evanl734
    @evanl734 9 дней назад

    What is the latency like? It looks like there is input delay or maybe delay from the screen. You would think the fpga itself would have almost no latency.

    • @dajoma36
      @dajoma36 8 дней назад

      It's been a long time since I've made this video, but yeah, there isn't much latency in an FPGA.

  • @egegoksu9557
    @egegoksu9557 Месяц назад

    Thanks

    • @dajoma36
      @dajoma36 Месяц назад

      You're welcome. Thanks for your thanks.

  • @thanatosor
    @thanatosor 3 месяца назад

    Why don't we use AXI-Lite ?

    • @dajoma36
      @dajoma36 3 месяца назад

      I believe the AXI is only for use with Xilinx Zynq chips, which are SOCs (System on a Chip) that include FPGA fabric as well as processor fabric. AXI is used for the processor part.

    • @thanatosor
      @thanatosor 3 месяца назад

      @@dajoma36 so If I want to use it on Artix-7, I need a soft-core CPU like microBlaze right ?

    • @dajoma36
      @dajoma36 3 месяца назад

      @@thanatosor That's a good question. Sorry, but I don't have any experience with microBlaze and using AXI at all. I only know about it that it is used with the Zynq SOCs.

  • @Alan96555
    @Alan96555 3 месяца назад

    Did you know that you have a problem in your code? 26C should be 79F and 27C 81F (If rounded up). Do you know how it could be resolved?

    • @dajoma36
      @dajoma36 3 месяца назад

      Not sure what you are referring to. And, as the system works as designed, I don't see that there is any problem. Maybe you could provide more details to support your claim.

  • @timmorgan3673
    @timmorgan3673 4 месяца назад

    Hi David - Another excellent video - Just what I was after - Cheers :)

  • @waqasbhaat
    @waqasbhaat 4 месяца назад

    Sir i have learnt verilog Please recommend me projects on verilog Without using fpga

    • @dajoma36
      @dajoma36 4 месяца назад

      Well, if you are just starting out with Verilog, I recommend these projects, which are fun and interesting: -Decoder -Multiplexer -Flip Flop -101 Sequence Detector -Gray Code Counter Then maybe do some state machines: -Traffic Controller -Vending Machine -Voting Machine Each of these projects you can write Verilog circuits for and then verify the designs using a testbench written in Verilog. The Icarus Verilog software, with GTKWave signal viewer, can be very useful for simulating your designs. You can find it here: bleyer.org/icarus/ Good luck and have fun! David

    • @waqasbhaat
      @waqasbhaat 4 месяца назад

      Sir i will do projects on state machine After completing these projects I will inform you Thankyou sir

  • @reddymooram6017
    @reddymooram6017 4 месяца назад

    Sir what about Constraint file

    • @dajoma36
      @dajoma36 4 месяца назад

      Not sure what you mean, but the constraints file (.xdc) is in the Github page for this project.

    • @reddymooram6017
      @reddymooram6017 4 месяца назад

      ​@@dajoma36thanks for the video sir successfully completed project

    • @dajoma36
      @dajoma36 4 месяца назад

      @@reddymooram6017 Awesome! I hope it was helpful to you.

  • @clutchoney
    @clutchoney 4 месяца назад

    Nice one it is. By the way, this code only works on basys3? My fpga is other one:(

  • @yusufbingul467
    @yusufbingul467 4 месяца назад

    this is what we needed for our project. Thank you

  • @thanatosor
    @thanatosor 4 месяца назад

    Nexys A7 is basically upgraded version of Basys3 😂

    • @dajoma36
      @dajoma36 4 месяца назад

      Yeah, pretty much. It has a bigger FPGA chip with more logic fabric, and more widgets.

  • @thanatosor
    @thanatosor 4 месяца назад

    Which one is worthy for beginner to learn FPGA ?

    • @dajoma36
      @dajoma36 4 месяца назад

      The Basys3 is your beginner board out of the two here. The price is much less, also.

    • @thanatosor
      @thanatosor 4 месяца назад

      @@dajoma36 so what's Nexys Video for ?

    • @dajoma36
      @dajoma36 4 месяца назад

      @@thanatosor The Nexys Video has a much larger FPGA and many peripherals for doing projects with video, such as HDMI. It is also a very expensive board compared to the Basys3.

  • @RevanasiddeshU-e5n
    @RevanasiddeshU-e5n 4 месяца назад

    Really nice effort from you sir, can you please provide the testbench for this?

    • @dajoma36
      @dajoma36 4 месяца назад

      Thank you. The testbench has been posted on Github in the project folder.

    • @RevanasiddeshU-e5n
      @RevanasiddeshU-e5n 4 месяца назад

      @@dajoma36 Sir There is no testbench in Improved version folder

    • @dajoma36
      @dajoma36 4 месяца назад

      @@RevanasiddeshU-e5n I put the testbench in the folder with the original video. The i2c master files are exactly the same for the older video and the improved version. So, look for the testbench in the folder for the first video I did on the temp sensor using the Nexys-A7.

    • @RevanasiddeshU-e5n
      @RevanasiddeshU-e5n 4 месяца назад

      That testbench is not working for this improved version

    • @dajoma36
      @dajoma36 4 месяца назад

      @@RevanasiddeshU-e5n I'm sorry, that is the only testbench i have for this.

  • @akhil_rana
    @akhil_rana 4 месяца назад

    What is pullup true meaning with respect to sda direction ?

    • @dajoma36
      @dajoma36 4 месяца назад

      When no device is actively pulling the SDA line low, the pull-up resistor ensures that the line is at a high logic level (Vcc). This is crucial because it defines the idle state of the bus.

    • @akhil_rana
      @akhil_rana 4 месяца назад

      Thankyou ..It was I was missing in my project

  • @muhammedalikaya268
    @muhammedalikaya268 5 месяцев назад

    sir, i 'm trying image load to vga monitor. In simulation, display variables are true but after the bitstream i can not see the image on the monitor. The monitor said 'no video signal'. What should i do? Can you help me, please?

    • @dajoma36
      @dajoma36 5 месяцев назад

      I would recommend doing some troubleshooting. Look into the hardware such as cable and cable connections. To check your digital signals, you could use a logic analyzer on the VGA signals and verify if they are working correctly. Other than that, I couldn't tell you. If your circuit is simulating properly, and the bitstream is generated it is an acceptable circuit. Analyzing the signals coming from the FPGA to the monitor could help you find an issue or let you know that the problem is not this part.

  • @timmorgan3673
    @timmorgan3673 6 месяцев назад

    Hi David - This is an excellent series of videos :) Dunno if you've come across Ross McGowan's "Design a CPU" series of videos or not ? These are also based on the "But How Do It Know ?" book, taking it to a 16-bit CPU, and then a Computer with a Keyboard/Monitor/Graphics Display. I found your RUclips website as I was looking for help with getting my "Computer" Verilog code (based on Ross's courses) onto a an FPGA (Basys 3) - Your stuff has proved to be really helpful - So: "Ta Much" :) Cheers, Tim.

    • @dajoma36
      @dajoma36 6 месяцев назад

      Hi Tim, thanks again for your comments. I have not heard of Ross McGowan's videos. I will have to check him out. Sounds like he took the CPU to a whole new level, and that sounds really interesting. Take care.

  • @timmorgan3673
    @timmorgan3673 6 месяцев назад

    Hi David - Interesting - I wasn't aware of the issues that can result from using tri-state buses - Anyways: I'm still using a tri-state bus on my "Computer" & all seems well on the Basys 3 with CLK_E/CLK_S running at 1MHz ... But "food for thought" - Ta much :)

    • @dajoma36
      @dajoma36 6 месяцев назад

      Hi Tim, interesting that you got the tri-state buses working. I was having trouble with them, and the comments I made about them came from my old college professor who said that to me. He is also the one who created the assembler for the project. Glad to hear everything is running well for you!

  • @timmorgan3673
    @timmorgan3673 6 месяцев назад

    A very clear explanation & demonstration of the Control Unit - Good stuff :)

    • @dajoma36
      @dajoma36 6 месяцев назад

      Thanks again for your comments! Glad it is helpful.

  • @timmorgan3673
    @timmorgan3673 6 месяцев назад

    Hi David - Another very interesting & informative video - Thanks again for putting all your FPGA Videos "out there" - Cheers :)

    • @dajoma36
      @dajoma36 6 месяцев назад

      Thank you for the feedback. I'm glad my videos are helpful and useful to people. Thanks for letting me know.

  • @denniswgm6526
    @denniswgm6526 6 месяцев назад

    Many thanks David, I learnt alot from your video.

    • @dajoma36
      @dajoma36 6 месяцев назад

      Thank you for the positive feedback. I'm so glad it was helpful to you.

  • @SouradeepSD
    @SouradeepSD 6 месяцев назад

    Greatly helped me for visualising my outputs of hardware accelerator I made for image processing for my mtech project. Thank you for the clear and precise explanation.

    • @dajoma36
      @dajoma36 6 месяцев назад

      Thank you for the positive feedback. I'm so glad that it was helpful to you.

  • @khevanapurohit4440
    @khevanapurohit4440 6 месяцев назад

    Can I do it with uart protocol? If yes how?

    • @davidmarion8930
      @davidmarion8930 6 месяцев назад

      No. The temp sensor is designed to communicate using I2C.

  • @jzie6615
    @jzie6615 6 месяцев назад

    Sir can you please help me with mu project... So basically I'm doing home alarm system using basys3 verilog code and my professor ask me to add buzzer and ultrasonic sensor when switch is on so how will i connect these two in breadboard... Using the pmod ports... And do I need any other components... Please help😢

  • @zainmohd7
    @zainmohd7 6 месяцев назад

    In your GitHub repository, the “flag.v” file is missing. Unable to run the simulation.

    • @zainmohd7
      @zainmohd7 6 месяцев назад

      Please respond, urgently need it.

    • @davidmarion8930
      @davidmarion8930 6 месяцев назад

      Ok. Sorry about that. Thanks for letting me know. As soon as I get a chance today I will put the file in Github.

    • @dajoma36
      @dajoma36 6 месяцев назад

      flags.v has been added to Github.

  • @diegodiaz585
    @diegodiaz585 6 месяцев назад

    Hello how would you turn on the decimal points to separate 100 sec , seconds, minutes, and hours

    • @dajoma36
      @dajoma36 6 месяцев назад

      Hi. You would need to include the decimal point for the segments. So, the segment would be bit-width of 8 [7:0] with seg[7] being the decimal point, and include the dp in the constraints file from the master XDC file. And you would only want to turn that bit on for the anodes/digits that you want to turn on the dp, not every digit.

  • @jzie6615
    @jzie6615 6 месяцев назад

    Can you please help me on connecting basys3 to adruino and from adruino with breadboard connect buzzer and ldr with led for some use in home alarm system

  • @abhishekss3560
    @abhishekss3560 6 месяцев назад

    Hey great video, but i am stuck at one issue, i think maybe you can help me?

    • @abhishekss3560
      @abhishekss3560 6 месяцев назад

      btw i have put an email to you! Hoping to hear back soon!

  • @timmorgan3673
    @timmorgan3673 6 месяцев назад

    Great stuff - Most informative - Thanks for putting it out - Cheers :)

  • @b213videoz
    @b213videoz 7 месяцев назад

    7:37 I do not understand line #22

    • @davidmarion8930
      @davidmarion8930 7 месяцев назад

      A case statement is a more elegant and concise way for checking conditions, like if/else. Inside the parentheses () is the condition to check. On line #22 the condition being checked is a concatenation of two signals into one signal. Concatenating signals in Verilog uses curly braces {} with the signals being joined separated by a comma. Hope this explains.

    • @b213videoz
      @b213videoz 7 месяцев назад

      @@davidmarion8930Sorry, no it doesn't explain. I do understand how CASE works what I do not understand how the address is being evaluated with {row, column} You just so casually skipped it over by throwing "concatenation". How ? Does it really do + ? Then it makes no sense address = row + column. I'm lost. address = row * <size of row> + column - that would make sense, but you use {row, column} and that seems to work.

    • @dajoma36
      @dajoma36 7 месяцев назад

      @@b213videoz Sorry, I guess I assumed that you might know what concatenation is. It is essentially joining the two signals into one. So, the bits of row and the bits of column will be joined into one, side by side, and evaluated as one for the CASE. It is not addition, nor multiplication, it is just placing them side by side. Example: if row == 0010, and if column == 1101, then the concatenation, i.e. joining, of the two, {row, column} = 00101101. Does this explain?

    • @b213videoz
      @b213videoz 7 месяцев назад

      @@dajoma36Thank you, David. Yes, of course I know what concatenation is but I know close to nothing about Verilog and FPGA programming in general 🙂 As it turned out in that particular case you had a merge of two 4 bit bit pieces into an 8bit one, which resulted in 4 bit shift to the left + 4 bit addition which effectively is the same as high_4_bits * 32 + low_4_bits, only much more efficiently of course. My point is that was a non-trivial piece of code deserving some explanation yet it was just skipped whereas some trivial and obvious bits were explained too well. Anyway your examples (I mean code) are extremely easy to follow, I just bought your paper book at Amazon, I do hope there are some good explanations there.

    • @davidmarion8930
      @davidmarion8930 7 месяцев назад

      Sorry I didn't explain everything. There's alot to cover in some of these videos, and I do try my best. I appreciate your feedback. Thanks for buying my book. I do hope it serves you well.

  • @b213videoz
    @b213videoz 7 месяцев назад

    Excellent stuff! Thank you, author - the best tutorial on the subject I've managed to find so far. 10:00 this is what I don't understand though: the wall as per your code should be on the left side, its X coordinate is something around 35 BUT in your video it's on the right side of the screen. HOW ?

    • @NVISH-kb4nc
      @NVISH-kb4nc 5 месяцев назад

      whole video is mirrored i think

    • @b213videoz
      @b213videoz 5 месяцев назад

      @@NVISH-kb4nc Yeah, I thought so, then the author clearly mentioned in some other video.

    • @NVISH-kb4nc
      @NVISH-kb4nc 5 месяцев назад

      @@b213videoz oh that’s great

  • @NaniGurrapu
    @NaniGurrapu 7 месяцев назад

    Their is no testbench code in GitHub

  • @pankajkumarsingh487
    @pankajkumarsingh487 8 месяцев назад

    bitstream generated but not working on board

  • @xmod2157
    @xmod2157 8 месяцев назад

    please make a video on 8bit risc V implementation

  • @dajoma36
    @dajoma36 8 месяцев назад

    @hardcode I received your message, but for some reason I cannot directly respond to you. As for your issue, why are you using 9600 baud? That is for a serial communications. All I did in the video was set up a simple 1Hz tick from the Arduino (LED blink sketch) to drive a counter on the Basys 3 FPGA, and then use a 7-segment display driver to display the hexadecimal value on 1 digit of the 7-segment display. If you are using serial communications at 9600 baud, then you are doing something different from what I did, and it is hard for me to know what your issue is. If you would like more assistance with your project, please email me with more details so that I can understand what you are trying to do and maybe help you out.

  • @Unknown101-ol7op
    @Unknown101-ol7op 8 месяцев назад

    worst

  • @Unknown_me_you_all
    @Unknown_me_you_all 8 месяцев назад

    worst video

  • @priyankamaharana3005
    @priyankamaharana3005 9 месяцев назад

    After giving the xdc file in vivado, the bit stream isn't generating. What should i do?

    • @dajoma36
      @dajoma36 9 месяцев назад

      Hi. Forgive me if I am being presumptuous. In order to make this work you need more that just the xdc file. You must add the Verilog files as source files and add the xdc file as a constraint file. Then, run synthesis, run implementation, and generate the bitstream.

  • @jermynlau6188
    @jermynlau6188 9 месяцев назад

    Hi, I found this this is amazing and useful!!! But I have another question, if I want to input more than 4 characters on the keyboard, what should I modify🤔🤔🤔 Thank you so much!!!

    • @dajoma36
      @dajoma36 9 месяцев назад

      You would need to make the FIFO capable of holding more than 4 characters.

  • @zongo579
    @zongo579 10 месяцев назад

    I just found your channel and have to say that I am a huge fan. I am still pretty new to Verilog so your channel has been really cool to check out.

    • @dajoma36
      @dajoma36 10 месяцев назад

      Thanks! I hope you can get a lot out of the content and that it is helpful to you.

    • @zongo579
      @zongo579 10 месяцев назад

      @@dajoma36 Your content has been EXTREMELY helpful. You have exactly what I was looking for with all your Verilog VGA tutorials. Keep up the great content 👍

  • @edwincrawford5619
    @edwincrawford5619 10 месяцев назад

    Hopefully you reply soon. But what are the parameters for the test bench? I created one but what are the inputs??

    • @dajoma36
      @dajoma36 10 месяцев назад

      Not sure what you mean. A test bench has no inputs. It simulates the inputs to the module under test. Here is the test bench I used for this project: github.com/FPGADude/Digital-Design/blob/main/Modules%20with%20Simulations/Sequence%20Detector%20State%20Machine/seq_det_101_fsm_TB.v

    • @edwincrawford5619
      @edwincrawford5619 10 месяцев назад

      @@dajoma36 I think I understand but my question is referring to rather or not does the test bench have any I/O port definitions

    • @dajoma36
      @dajoma36 10 месяцев назад

      @@edwincrawford5619 No. A test bench does not have I/O ports.

  • @hammadmalik6135
    @hammadmalik6135 10 месяцев назад

    How can I contact you?

    • @dajoma36
      @dajoma36 10 месяцев назад

      You can contact me through the email address on my About page.

    • @NaniGurrapu
      @NaniGurrapu 7 месяцев назад

      We can't find email address

  • @p0keyy
    @p0keyy 11 месяцев назад

    Great content, thanks for this! Not sure if you'll see this but I'm trying to better understand how the code works with the animating and to do so I was challenging myself to try and make the box endless loop around the display area but was unable to do so after many hours of attempts. I am failing to understand where the square starts as I thought the x and y registers determined that but with my code whenever I reset, it would start on the bottom left of my screen, likely something to do with the code I modified to detect the borders. My idea was just to utilize the same border detection you had but I would want to start in the top left and then just only have movement either vertically or horizontally, no diagonal. So I just made it so whenever a border is hit, I would set the horizontal or vertical next registers to 0 and the other to the pos or neg where needed.

    • @dajoma36
      @dajoma36 11 месяцев назад

      Sounds interesting. I don't see a reason why your idea of having the square bounce around the screen wouldn't work. Keep working at it, and I'm sure you will find a solution. Thank you for the nice comments. Happy Thanksgiving!

    • @p0keyy
      @p0keyy 11 месяцев назад

      @@dajoma36 Thanks for the words of encouragement Just unsure of why whenever I introduce a new condition for a border it will only detect that condition and endless loop from there. For example I had the top border condition and then it would start top left and go down Then I introduced a condition for the bottom border then it would only start from bottom left Hopefully I can figure it out Have a great thanksgiving aswell!

  • @hamzainam6211
    @hamzainam6211 11 месяцев назад

    Excellent work form your Side.

  • @cyrilkumpuckal1592
    @cyrilkumpuckal1592 11 месяцев назад

    i mean not once have one of these codes worked for me

    • @dajoma36
      @dajoma36 11 месяцев назад

      I haven't messed with this project since doing the video for it. I just broke out the Basys3, my VGA screen, opened Vivado, created the project files, copied all the code over from the GitHub repo, ran synthesis with no problem, ran implementation with no problem, generate bitstream with no problem, and the project is working just fine for me. I just typed "HI" on my screen from using the switches and buttons on the Basys 3. I am sorry that you are having problems. I guess, just make sure that you have copied over all the code correctly, including the Verilog files and constraints file. FYI, I am using Vivado version 2023.1.

  • @fmm5322
    @fmm5322 11 месяцев назад

    I watch your videos regularly. I have a simple question. Suppose sensor supports 5MHz spi interface. That mean sclk is @5MHz. If we set output data rate of sensor @100 HZ how we make sure that we are logging the correct output samples during spi read from sensor? Because we are sampling @poseedge of sclk

    • @dajoma36
      @dajoma36 11 месяцев назад

      Sorry, but I'm not really sure you mean and what you are asking. To be honest, I haven't done anything with SPI except for that video.

    • @fmm5322
      @fmm5322 11 месяцев назад

      @@dajoma36 ok no problem. How can we check the code without real sensor? Any emulated idea.? How to generate miso data without sensor.

    • @dajoma36
      @dajoma36 11 месяцев назад

      @@fmm5322 You should be able to test the circuit without a real sensor using a test bench module. To generate the sensor data, you would need to find out how the data is formatted, and then use that data format in the test bench script to stimulate the circuit, along with the other inputs for the circuit, such as clock, reset, etc.

  • @MEGLADON4U
    @MEGLADON4U Год назад

    Is there any way I could not have the decoder initially set the value of dec_out to "0000" once the program starts? Could I set dec_out to null initially so that when the program starts there is nothing being driven out of dec_out until a button is pressed?

    • @dajoma36
      @dajoma36 Год назад

      Sounds very feasible to me. I don't see why you couldn't do that.

  • @alexbeckes3389
    @alexbeckes3389 Год назад

    great video. I was stuck on how to control the seven segments individually and this was the only video i found that explained it