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how we can do for implementation can u plz make a video?

Thank you for sharing your knowledge, if you show the implementation, then its helps a lot, thank you once again.

Could you share the project codes?

i am continuously noting that you are using ZYNQ IP without any reason just to common clock with other signals. there is no sense to use it.

CAN YOU MAKE BY USING ZEDBOARD

hi could you please make video for 12 bit DAC ,configuring spi interface

@marwanal-yoonus280 0 seconds ago Dear Sir Please, I have a problem during reading the status of an output switch on Zybo Z7-10. I use Vitis to program the Zynq processor with Gpio connected to a slid switch. I make the switch (input2) status as a condition as shown in the program below if (D == 1) ; The following program works only when the input2 signal that was connected to Gpio IP starts from ("1") but the program does not work when input2 signal starts from ("0"). ////////// while (1) { D = XGpio_DiscreteRead(&input2, 1); // input2 from a slide switch if (D == 1) { sum_all = XGpio_DiscreteRead(&input, 1); // input is a 32-bit data printf("%x " , sum_all); sleep (1); } else { XGpio_DiscreteWrite(&output, 1, 0); // output is a LED printf("No_Signal "); sleep (1); } } ///////////// i.e. the program works only when I change input2 from "1" to "0" but does not work when the input2 start changes from "0" to "1".

I am new to FPGA .Can i get the code as well as description such that i can learned about each line

pls send the c code

Can you share code

Hi, How can we get the code you used? Can please you send us? Thanks😊

Sir can you share me code

really appreciate the amazing work, i would like to ask for the code please. Thanks again for the effort.

Hi, can you send me the code plisssssssssssssssssssssssssssssssssss, im in a hurryyy , plissssssssssssssssssssssssssssssssssssssssssssssssssssssssssssssssssssssssss

how to control amplitude of sine wave?

Could you share code of the project?

is there any way i get this code and gui file?

Terrible video

Hi sir, great content it helped me a lot. Is there way to reach out to you, as have some doubts in procedure and it be greartly indebted to you for your help.

hi

I want to transfer or send the hexadecimal file via ethernet TCP protocol, how to change the code by using LWIP TCP server and client processor

hey thankyou for the amazing video !!!!! you really putting a very good efforts in making this project . thank you for sharing this video . could you please provide the code it would be a great help.😊

Audio is nul for this video.

Hello,Could you please send me a copy of this Hello-word TCP example?

❤🎉🎉

Thanks for the video , could you please share the code?

Hello@Advabced FPGA & Digital Electronics.Can you send the code ??

Well explained. Only thing I am having a problem with is the bit width coming from your DDS compiler. In your previous video, the DDS compiler was only 16 bit width but in this bit it was changed to 32 bits. I do not seem to have the option to configure the DDS to 32 bits.. maybe we have a mismatch in versions of Vivado? I don't believe my output is correct with only the LS 16 bits being inputted into the 32 bit FFT data port. Would like to hear your input.

Hello can you please share the code

Could you pls share the code

Please send code, thank you.

another great video👍👏 thanks i have two questions 1- can you explain the calculations you did at the end of the video to get 4085 ? 2- why you used m_axis_tuser and not m_axis_tdata ?

code

Hi, I watched some of yours FPGA movies and I was wondering if you have github with source files :)

can i get the code

Hello! Will the flash retain the loaded program after i disconnect and reconnect the usb cable? Could you please say?

hello @Learning Advanced FPGA , i need your help with the ethernet connection establishment , can you pls send me the "xaxiemacif_physpeed.c" ,it would be very helpfull to me.

Can you please share the codes.

where is the code?

Please share the code.

could you please share the code? thanks

Is it possible to do image convolution using FIR compiler IP Core?

Is there anyone who is interested in generating sinusoidal without using Zynq and in VHDL not Verilog?

I cant find sdk in the software ? 🙄

Thank you for sharing. could you share codes please?

Thnak you so much for this video, can you please share the code ?

Could you pls give the code

Can you please send the code asap?

Excelent video, could you share the code please?