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One of the best videos to understand PCIE enumeration

this series is gold !

This is the best presentation I have found so far on this subject matter to date. Thanks for putting in the time to spread this knowledge!

nice.video is mot clear .ca you please host again

Very well explained!!! You explained the memory translation sequences in a simple and clear manner. Thanks a lot.

great lecture

شكرا لك

best explanation .

Could you please also provide some insight into MMIO with SR-IOV and other dependency to have SR-IOV VFs configuration with virtual machine.

It’s a very informative video. Thanks a lot.

Could you please explain how you set up the DOS Code debugging? Are you simply logged on to the "usermode" of DOS and it lets you directly access BIOS level constructs? Or did you set up something in between? Would love to know if this can be done in some way with modern OSs as well!

How does the port mapped I/O requests (via the In/OUT instructions) reach the PCI config registers in the first place? Do the motherboard vendor solder the buses coming out of the CPU into the system agent in such a way that this would always be the case (possibly following the PCI/PCIe specification?) ?

In case of PCI (could be PCIe as well, I haven't studied that far), the BIOS directly accesses the PCI BARs directly via port mapped I/O and sets them up with proper values to map different memory/I/O chips to different ranges in the system address map. But how does this port map I/O BAR access happen in the first place? Is the address bus soldered on the motherboard to connect to the PCI chipset in such a way that specific port mapped I/O access request always reach these BARs (according to the PCI specification)?

Really hope this great series could continue. It's a treasure.

It's really helpful to see with my own eyes. Thank you sir!

In the eye of a CPU core, the world is just a bunch of addresses, be it memory or IO addresses. Just like a Turing machine viewing the boxes on a paper tape. It is BIOS' responsibility to properly program all the system agents and downstream decoders on the platform to route the transaction targeting a certain address to the right destination. Be it DRAM, PCI-E endpoint device, etc.

This is a superb explanation on memory mapped i/o , always go through this series for quick refresher on system side topics .

Awesome & great explanation

clear !! nandri

Hello Sarathy, are you able to help me out with the full breakdown of MCFG Table please ?, I am unable to locate any manual after scouring online for days. Thank you so much.

Sir quick question - When we power ON, the execution starts at FFFF FFF0h (4GB-16) bytes but the CPU will operate in real mode where it can access 16bit address space then how it can access FFFF FFF0h which is 32bit address space?

Thanks so much sir from Maharashtra

Excellent explanation. I was trying to dig through so many books and info but was unable to get the exact info I needed. But your videos provided most of the info I needed.

Best video ever, so clear

Thank you so much for this comprehensive series. The knowledge of those topics is spread over lots of sources and specifications so it's very convenient that you managed to summarize it in this series, that was an awesome contribution!

DMI = Direct Media Interface

Thank you for your efforts in making this video. It helped.

Excellent Knowledge sharing videos. This is great knowledge Sarathy that you have gathered and now sharing with everyone.

Thanks and appreciate the knowledge shared in a clear and concise way. This series is a great resource to get started with a clear understanding of the enumeration of PCIe devices.

loving the videos keep up the good work . Got clear idea on computer architecture

Thanks sarath for the detailed description of POST operation in the system .

excellent explanation

Clear & Simple explanation. Than you @Sarathy Jaykumar!

is this flow also Includes POST?

Very good explanation to understand the basics of config space handling in PCIe

Re. writing (0xFFFF_FFFF) and reading back the BAR to figure out the size of the (memory) region the device requests to be mapped to system address space, note the following with the example of the device requesting 4KB space (4096 bytes) 1.Lower 4 bits of the BAR are read only, i.e. each BAR is 32 bit , out of which first 4 bit 3:0 are always Read Only. 2. It would be wise to save the BAR value before writing to it. 3. Write 0xFFFF_FFFF & read it back, value read = 0xffff_f00X 4. Clear the last 4 bits - they are read-only, typically will be read back as 0's after step (3), value read = 0xffff_f000 5. Invert the value in (4) and add 1: value = 0xfff + 1 = 0x1000 = 4096 Due to the nature of the above mechanism, the min space the system allocates to device memory will be 16 bytes - corresponding to the 0's in bits[3:0] i.e. if for some reason the device requests anything less than 16 bytes, it will still be allocated 16 bytes in the system address map. Practically this hardly happens given that modern systems with 32-bit registers & addressing in place; but good to be aware of if one runs into a resource constrained scenario

a great series! I would watch a dozen more of these in a heartbeat! if you have them recorded, please release them :)

I got a doubt Enumeration will done in GEN1 L0 or at max data rate if it supports?

Is there a book detailing more information on this subject that you learned from? Where did you get this information from? Like the video by the way, very detailed and conveyed in a manner everyone can understand!

I got a doubt why Type 0 config space has 6 BARS and Type 1 has 2 BARS

Nice and clear explanations from an excellent engineer. Thank you :-)

great series.. Thank you so much

Finally I understand the logic of MMIO. THANKS!

This is so precious. Please CONTINUE! THANKS!

It is a such a good deed.

This is a very good PCI refresher series! You mentioned that the root port stores the range of MMIO addresses assigned to downstream devices. During BIOS, the enumeration process can make sure that all downstream devices get consecutive MMIO spaces assigned. The range values in the root port can be accurately programmed. What happens if at a later stage, one of the downstream devices is removed and another one, which requires significantly more MMIO space, is hot-plugged in? The MMIO space assigned to this new device might not be adjacent to other sibling device. How does the root port store the (now fragmented) range?

plz continue this series

thanks for good video

Any source for PCIe code understanding?

Excellent videos