Видео

Problem Session 4 - Solving the final Exam of T211 (Q6 and Q7)

Problem Session 3 - Solving the final Exam of T211 (Part 1: Q5-2a)

Problem Session 3 - Solving the final Exam of T211 (Part 1: Q5-1)

Problem Session 3 - Solving the final Exam of T211 (Part 1: Q4)

Solving the final exam of T211 (Part 3)

Solving the final exam of T211 (Part 2)

Solving the final exam of T211 (Part 1)

Review class.

Verilog Modeling of Shift Registers with and without Shift Control. Modeling a Multi-Function Register. Modeling Counters and their Testbenches. Modeling a Clock Frequency Divider.

Optimized Implementation of the Multi-Function Register Example of Last Lecture. Sequential Circuits Modeling in Verilog. Modeling Latches and D Flip Flops. Synchronous Vs Asunchronous Control Inputs. Behavioral Modeling of Finite State Machines. Testbenches of Finite State Machines. Examples. Modeling n-bit Register with Parallel Load Function.

Registers and Counters. Parallel Load n-bit Register. Parallel Load n-bit Register with Load Enable Synchronous Input. Shift Registers and Timing Them. Applications of Serial In Parallel Out (SIPO) Registers: Store Serial Arithmetic Compuations and Sequence Detection. Parallel In Serial Out (PISO) Register.

Universal Shift Register. Ripple or Asynchronous Up/Down Counters. Synchronous Up/Down Counters. Examples.