Codasip
Codasip
  • Видео 119
  • Просмотров 25 277
With great power comes great responsibility - Customizing your processor with verification in mind
Codasip Studio Product Manager Filip Benna discusses how to customize your processor whilst keeping verification in mind. This talk was given at the 61st Design Automation Conference.
For years, Codasip Studio has been the go-to toolset for generating both RTL and software development tools from a single processor model. The latest version, Codasip Studio Fusion, enhances this core capability and introduces a layer of segmentation. It allows you to configure the core from predefined options, create custom instructions within set parameters, or design with complete freedom.
Просмотров: 152

Видео

A short overview: Codasip Studio Compiler
Просмотров 542 месяца назад
CTO Zdenek Prikryl gives a quick overview of the Compiler capabilities of Codasip Studio
A short overview: Codasip Studio Profiler
Просмотров 432 месяца назад
CTO Zdenek Prikryl gives a quick overview of the Profiler within Codasip Studio
A short overview: How to relate generated RTL back to CodAL
Просмотров 542 месяца назад
A short overview: How to relate generated RTL back to CodAL
A short overview: Getting started with Codasip Studio & CodAL
Просмотров 912 месяца назад
A short overview: Getting started with Codasip Studio & CodAL
RISC-V Summit Europe highlights
Просмотров 1702 месяца назад
RISC-V Summit Europe highlights
DAC Demo: AI Inference for anomaly detection on an embedded RISC-V core
Просмотров 1812 месяца назад
Solutions architect Troy Jones showcases the latest Codasip demo live from DAC 2024.
RISC-V Summit Europe day 1
Просмотров 1152 месяца назад
RISC-V Summit Europe day 1
Codasip Studio Demo
Просмотров 2402 месяца назад
Codasip Studio Demo
How do vector length agnostic architectures work?
Просмотров 3894 месяца назад
A short overview of the similarities and differences between SIMD and Vector approaches, and a description of how the RISC-V Vector code is portable between machines of different Vector lengths.
Toby Wenman talks about Vector load/store segment instructions
Просмотров 2034 месяца назад
Our UK design centres in Cambridge and Bristol were set up in early 2022 to develop high performance, low power embedded and application CPU cores from scratch. They are focused on creating clean-sheet in-order and out-of-order designs, and need people who can establish high quality working practices as they explore new ground under the guidance of Kalvin Williams, the Senior CPU Design Manager...
Codasip Demo - Accelerated DSP on a Customized RISC-V Core
Просмотров 1564 месяца назад
Alexey Shchekin demonstrates the Codasip L31 (3-stage 32-bit RISC-V) processor on FPGA that runs several DSP algorithms: FIR filtering, FFT, Viterbi decoding. The processor is customized with Codasip Studio and enhanced with hardware accelerators that improve the performance of these DSP algorithms.
Codasip at Embedded World 2024 - meet our partners
Просмотров 2124 месяца назад
Codasip at Embedded World 2024 - meet our partners
Embedded World 2024 day 2 highlights
Просмотров 944 месяца назад
Embedded World 2024 day 2 highlights
CHERI Demo at Embedded World 2024
Просмотров 1264 месяца назад
Andrew Lindsay demonstrates an example of our award winning CHERI implementation at Embedded World 2024
Embedded World 2024 day 1 highlights
Просмотров 1104 месяца назад
Embedded World 2024 day 1 highlights
Carl Shaw - CHERI protection & software
Просмотров 1885 месяцев назад
Carl Shaw - CHERI protection & software
Carl Shaw - Compartmentalization CHERI
Просмотров 885 месяцев назад
Carl Shaw - Compartmentalization CHERI
Ben Fletcher - CPU performance modelling
Просмотров 4975 месяцев назад
Ben Fletcher - CPU performance modelling
Carl Shaw - What is CHERI and why is it necessary?
Просмотров 3575 месяцев назад
Carl Shaw - What is CHERI and why is it necessary?
Jamie Melling - Understanding RISC-V virtual memory
Просмотров 6885 месяцев назад
Jamie Melling - Understanding RISC-V virtual memory
Tariq Kurd - Efficiently managing tagged memory for RISC-V
Просмотров 1755 месяцев назад
Tariq Kurd - Efficiently managing tagged memory for RISC-V
Tariq Kurd - A730+CHERI
Просмотров 2265 месяцев назад
Tariq Kurd - A730 CHERI
Codasip at RISC-V Summit US 2023 - Day 2
Просмотров 679 месяцев назад
Codasip at RISC-V Summit US 2023 - Day 2
Codasip at RISC-V Summit US 2023 - Day 1
Просмотров 639 месяцев назад
Codasip at RISC-V Summit US 2023 - Day 1
Codasip at Design Automation Conference 2023 DAC
Просмотров 139Год назад
Codasip at Design Automation Conference 2023 DAC
RISC-V customization demo: AI-based image denoising
Просмотров 195Год назад
RISC-V customization demo: AI-based image denoising
RISC-V Summit Europe 2023 - Codasip summary
Просмотров 127Год назад
RISC-V Summit Europe 2023 - Codasip summary
Codasip’s approach to custom compute
Просмотров 352Год назад
Codasip’s approach to custom compute
Architecting ambitions with custom compute #ew23 #embeddedworld
Просмотров 479Год назад
Architecting ambitions with custom compute #ew23 #embeddedworld