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Hlo . register counter ku video podunga . sis enaku knj clear a explain panringlaa

Mam u didn't declare the variable i

Super mam

Mam which are you using mam please make how to download it

Mam apdiye sv concept assertion functional coverage request pannirunthe upload panna solli and uvm start panna effective ha irukum😊 always be thankfull mam

Always great lesson for beginners easy understanding mam please keep going like this✨

Mam EC(advanced communication technology) course ku usefull aa erukkuma mim??

replication operator la bits um replicate aairuma n vachu or anything else

Can you explain about dynamic casting ? what is the use case ? what if we failed to use it?

Mam enakku be vlsi design syllabus anna university venum maam

@13:22 ..mam ninga tr2 ku object create panalaila...aprem epdi 2 value assign aagum.....as u said null pointer dereference error dhana varum?..can you pls explain me mam

Waiting for more than 1 month for system verilog assertions topic

Mam Ece la vlsi engeenering easya irukumaa illaa tough ahh mam

Private intitute irukka

Mam still waiting for assertion and functional coverage konjo sikro potingana romba useful ha irukum😊

Pls post uvm videos also mam

Mam program run pannurathuku compiler pathi solluga. Please mam.

Eagerly waiting for assertion and functional coverage video mam, please koncham sikramave upload pannunga 😊

System verilog assertion video please

Mam, Ethavathu Certification Course Teach Panringala ?

Instead of using unique can we use rand c also to generate unique value so that if we r using rand c means we wont get repeated values

MAM , BACKEND VLSI PLEASE TELL ABOUT IT AND TUTORIALS TOO.

Thank you for your constituency uploading videos about sv mam nandriiii..... Mam please system verilog assertion and functional coverage video please

As a subscriber noticed an issue in this video, and pinged us in Instagram. we have Updated Reuploaded it. ruclips.net/video/Z9QuOgc3WPk/видео.html Please use this video for better understanding. Thank you!!!

Mam,i am a mechanical engineer 2022 passed out,no experience,naan epdi pcb design and vlsi design department la varuvathu maam?

Mam na vlsi and ece department pathi unga kita pesanum. Intha year na clg join pananum.ece choose panalamnu irukan. So konjam doubt iruku.

Weekly 2 to 5 videos podunga mam.. Nala iruku unga video.. Super mam🔥... But ninga monthly once podringa.. Konjam neraya podunga mam

Mam inum video podunga mam🙏🙏🙏🙏🙏🙏🙏🙏🙏🙏🙏🙏🙏🙏🙏🙏🙏🙏i will see ur video

2^16 😂 is not 256 right. 2 ^8 is only 256🎉❤

mam now in 2024 it is important to learn vhdl or verilog

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😂😂😂😂 .*🎉❤

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Great explanation. Please post UVM videos, it would be very helpful mam

module carry_look_ahead_4bit_tb; reg [3:0] a,b; reg cin; wire [3:0] sum; wire cout; carry_look_ahead_4bit dut(.a(a), .b(b),.cin(cin),.sum(sum),.cout(cout)); initial begin $dumpfile("dump.vcd"); $dumpvars(1); a=0; b=0; cin=0; #10 a=4; b=2; cin=0; #10 a=7; b=5; cin=0; #10 a=3; b=5; cin=1; #20 $finish; end initial $monitor( "A=%d, B=%d, cin= %d, sum=%d, cout=%d,A=%b, B=%b, cin= %b, sum=%b, cout=%b", a,b,cin,sum,cout,a,b,cin,sum,cout); endmodule this is the testbench I have a doubt that can I assume any values for a,b,cin

Mam na epa than b.e electrical engineering la vlsi eduthurkan enaku syllabus enna nu theriyala aprm enna la engineering exam lam attend panna mudiyuma pls rly mam

Please upload how to write a Test bench in system verilog

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Very useful Mam....🤝🏻

Akka pls continuous ah video upload pannuga. Romba helpfull ah iruku. UVM concept quick ah podunga❤😊

please upload more constraint interview questions like this mam ,your work is so much great. now i able to understand the constraint mam thank you so much

Please upload functional coverage

Dollar display and dollar monitor ku difference sollunga sister Tamil la....simulation result la ena changes nadakum nu sollunga

Mam..pls.give some guidance about available open source software for vlsi project.

8:58 Two methods I have mam, please review it 1. val[i] = fact ((( i + 1 ) * 2 ) - 1 ) 2. val[i] = fact ( i + ( i + 1 ) )

Hi Mam. If we do right shift will it generate only the One's? constraint c1 { data == 1 >> shift ; }

Please we need a regular videos ,atleast 4 videos in a week mam and pls post videos in Interprocess Communication SystemVerilog Program Block SystemVerilog Clocking