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the matrix multiplication code files (mat_mult.vhd and constraintx.xdc). It is a matrix multiplication between A and B (32x32) x (32x32) floating-point 64bits, and it only uses one multiplier and one adder by using a sequential scheme and distributed memory. It uses clock 375 Mhz from PLL (PLL clock input from internal clock: 125 Mhz). Herewith the result of Chipscope. From the above figure, we can see after the matrix multiplication is done (signal done_OBUF at number 1 is '1'), the counter ax shows 67615, which means to calculate the matrix multiplication's calculation needs 67615 clock's period. Therefore, the execution time is (1/375 Mhz) x 67615 = 180 microseconds. The matrix multiplication's results (matrix C) are saved into distributed memory. The matrix's result C has 32x32 entries/elements. In the above figure (please find the red box number 3 at figure), the number 3 is the example of a data result that read from memory at address 0 (data result from address memory 0 : 7afb800000000000, it is a floating-point 64 bits which follows the floating-point rules in this website: hardwaredescriptions.com/floating-point-in-vhdl/).

library ieee; -- component #1 use ieee.std_logic_1164.all; entity test1 is port( X: in std_logic; Y: in std_logic; F2: out std_logic ); end test1; architecture behv of test1 is begin process(X,Y) begin F2 <= X or Y; -- behavior des. end process; end behv;

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