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Thanks for the clear explanation! Very helpful.

Impressive content, TechSimplified TV. Looking forward to your next upload. I clicked the thumbs up icon on your video. Keep up the fantastic work. Your detailed step-by-step approach to constructing the SEOS Norgate was enlightening. How do you recommend addressing potential discrepancies in the output when scaling this design for larger circuits?

nice explanation. Great job. can you share PPT

TechSimplified TV, your content is really helpful! Keep it up. Can you please share the slides as well ?

Your explanation and information is very nice, i have doubt Where exactly we r using these isolation and retention cells ?

Can we use retention cells and isolation cells with same voltage domains ?

Please have next guest vinay Chadha

What a great time to live we are having an electronics expert of 5 decades in the podcast 😮

It is a wonderful podcast sir.

Really a valuable podcast .

can you explain if we close timing in slow slow but still see timing violations in fast fast corner what are the possibilities

Wonderful podcast.

Thank sir

Thanks so much sir for the interview, I am enjoying the topics discussed. I have a question that I would like to ask. In around minute 7, a question about on-campus and off-campus opportunities have been addressed. You stated that off-campus is the correct approach and that on-campus has to be abolished. If I understood correctly, you are talking about employment and job opportunities and you are saying that the reason why off-campus is a better approach is because what students really care about during their college years is getting high scores rather than understanding the subjects well. If I understood correctly, you are not talking about education in off-campus is a better approach than on-campus in terms of learning process and its outcomes as facing the instructors in person is the best way of learning from them. This is what I understood, kindly correct me if I am wrong. Thanks once again and I hope to see more of such interviews.

Hello viewers! Thank you for watching the podcast live and asking questions. Some questions we have already discussed. Listen carefully. Some other questions regarding what to do after completing course and regarding career gap , please ask directly Balajee Sir in his channel . Watch Balajee Sir's videos : www.youtube.com/@@etalvislearning He is very helpful and dedicated for students. Help him to help you and guide you.

Sorry may I ask is verilog-a can create DRAM array for computing in memory ?

Very informative ❤

Hi , I am not able to play this video

We are blessed to access the resources from your experience sir, thank you so much!

He is the best teacher i've ever seen!!!.thanks to sir balajee seshaadri

Waiting for your continuation Mr. Balaji ji.

I have never seen a teacher / anyone who have not only understand but also accepted the nature of current generation students . Mr. Balajee Seshadri is a great learner and great teacher. With more & more people like him .... I guess engineers will gain true knowledge & skill and will be more respected as other professionals. Thank you both for focusing on the most important aspects that we,students need .❤

Happy to see sir, Expressing his thoughts and showering the wisdom.

Good evening mam.My question to sir is that " Is doing M.Tech/M.S Important". If yes, How? please expalin in brief sir .🙏🏼🙏🏼

This is a Great Session for Every Learner🤩

Thank you for the amazing session! It was incredibly insightful, and I truly appreciate Balajee Sir's effort despite the unexpected power cut. Looking forward to the rescheduled session to continue where we left off. It would be great if this could be addressed next time. Kudos to the team for organizing such engaging content! I totally agree with what sir has told. But at the same time the env, current education style & quality also has huge impact. Waiting for next...! Thank you sir & Thank you TechSimplifiedTV.

Yes

I learned alot of embedded related topics from sir through his lecture videos ,i am grateful to be an student of him,where sir gives proper guidance to every student who aproched him .

Clear explanation, thank you. What is the difference between makefile and config file (.cfg) ?

Hey viewers! Sorry we had to close the session unexpectedly! There is a power cut issue @ Balajee Sir's end. He made it sure he wants your feedback and questions. Please write down in comments. We will try our best to reschedule the session and will start from where we stopped. It was an amazingly engaging session ! Thank you Sir for your valuable insight!

Any reason why the FEOL plot is not: A) a rectangle: why does SF corner have a slightly faster NMOS than SS and a slightly slower PMOS than FF? B) a square: why is F of NMOS faster than F of PMOS? I will appreciate you addressing these queries. Thanks!

good knowledge

what about the leakage of transistor M2 shown in slide at time stamp 31:25

what is the meaning of ON resistance ? ON resistance of NMOS and PMOS

Sir as a Masters student in VLSI, which all scripting language should i study for placement purposes in India

Contact Kunal Ghosh for Internship and/or Sqadron Board : Mob no. 9686428727 Email - kunalpghosh@gmail.com

1:14:00 can I know more details about it sir?

Kunal ghosh sir 😯i have done internship in his vsdsquadron

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Good class

What can i use company name if im student

I'm currently using Ubuntu 20.04 version , the installation is stuck at final processing, downloading 2024.1 package could you please help ?

Excellent video!! Keep them coming!👏👏

at 19:05, I got this (my yosys 0.33 ) yosys> dfflibmap -liberty cmos_cells.lib 5. Executing DFFLIBMAP pass (mapping DFF cells to sequential cells from liberty file). cell DFF (noninv, pins=3, area=18.00) is a direct match for cell type $_DFF_P_. cell DFFSR (noninv, pins=5, area=18.00) is a direct match for cell type $_DFFSR_PPP_. final dff cell mappings: unmapped dff cell: $_DFF_N_ \DFF _DFF_P_ (.C( C), .D( D), .Q( Q)); unmapped dff cell: $_DFF_NN0_ unmapped dff cell: $_DFF_NN1_ unmapped dff cell: $_DFF_NP0_ unmapped dff cell: $_DFF_NP1_ unmapped dff cell: $_DFF_PN0_ unmapped dff cell: $_DFF_PN1_ unmapped dff cell: $_DFF_PP0_ unmapped dff cell: $_DFF_PP1_ unmapped dff cell: $_DFFSR_NNN_ unmapped dff cell: $_DFFSR_NNP_ unmapped dff cell: $_DFFSR_NPN_ unmapped dff cell: $_DFFSR_NPP_ unmapped dff cell: $_DFFSR_PNN_ unmapped dff cell: $_DFFSR_PNP_ unmapped dff cell: $_DFFSR_PPN_ \DFFSR _DFFSR_PPP_ (.C( C), .D( D), .Q( Q), .R( R), .S( S)); 5.1. Executing DFFLEGALIZE pass (convert FFs to types supported by the target). Mapping DFF cells in module `\counter': mapped 3 $_DFF_P_ cells to \DFF cells.

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