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Please send me the check list. Thank you

Send me the checklist

Please, send me the checklist. 😉

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Please send me the checklist

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Theoretical question: can the same circuit diagram be used with KT805b transistors?

Send me the checklist. I really appreciate fellow engineers who recognize that all the knowledge comes from the mistakes!

Star ground is often misapplied, and almost certainly the ground trace making up the "star" shouldn't be really skinny and narrow. However there are situations where you need to transmit a single-ended, audio-frequency, microvolt-level signal adjacent to some big power-hungry thing switching a lot of current and it's these cases where the star ground is a useful tool. For example, you might have an audio preamp going to a 16-bit ADC adjacent to a powerful CPU. For 1v amplitude and 16-bit resolution, one LSB is 15 microvolts so the 16-bit audio signal is fairly sensitive to crosstalk and common-mode effects. In this example, assume the CPU is taking interrupts or doing some other work at audio frequency rates, e.g. 60 Hz display refresh or 1 kHz USB SOF interrupt. Therefore its power consumption will vary correspondingly as the CPU wakes up to handle the interrupts and goes back to sleep. On something like a 12x12 inch board with a typical 1/2 oz copper ground plane and even a modestly powerful CPU, audio-frequency current driven across the system ground plane as the CPU wakes up and goes back to idle create audio-frequency potential differences across the digital plane which exceed that 15 microvolt noise threshold to actually get 16-bit quantization. Now in the presence of this small but significant ground shift, how do you communicate your single-ended, 15 microvolt sensitivity signal from the preamp to the ADC without it getting screwed up due to ground shift between the preamp and ADC? Well, one technique to solve this is to locate the preamp and ADC ground pins right next to each other. Very small distance between the ground vias means basically no potential difference. Another technique is to lay out the board such that area of the ground plane where your CPU's switching is creating is creating potential differences just does not overlap with the path between the ground pins of your analog chips. That way the CPU's switching currents may be making a potential difference in the part of the plane between the CPU and its VRM, but your analog signal processing is elsewhere on the board and is unaffected by ground shifts caused by the CPU. (Third idea: build the whole CPU out of constant-current logic like ECL. Haha just kidding!) However those techniques only go so far. What if there are some non-negotiable thermal or mechanical constraints forcing you to put the CPU and analog circuitry such that the CPU's induced ground shifts do indeed overlap the analog circuitry? At some point of increasing mechanical constraint, quantity of sensitive analog circuitry, and audio-frequency dI/dt from big switching SMPS or CPU or whatever, star routing of the ground becomes a useful tool if you apply it with sufficient care and understanding. The same is true of splitting the ground plane. It's hard if not impossible to eliminate capacitive coupling between adjacent planes, but as with the star ground, I can imagine combinations of electrical and mechanical constraints where you basically need two ground planes. Of course make sure to move signals across the two with optical isolation, transformer to create a "true" differential pair, "iCoupler," etc.

Great video! When you say, "Make sure to have a ground-plane without obstructions", does that include vias? If so, how are you supposed to take advantage of the other layers of the board (i.e., if layer 2 is my ground plane, how do I get to layers 3 and 4 without vias)?

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👍🙏 Thank you! 😊

Pleases send me a checklist.

Send me the chicklist

Send me the checklist

Send me the checklist

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Please send me your book. Well thought out with practical demonstrations

Send me the checklist! I would love that wealth of knowledge

Send me the checklist

Send me the checklist.

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I'm pretty conflicted on the vias allowing the electromagnetic energy to flow. I have also believed this, but if you review Lee Ritchey's Right The First Time, Vol 1 or 2, he will tell you that there isn't much evidence of this. Rather the more important thing is that you have propper interplane capacitance to allow for the currents to return by displacement currents rather than conducting currents. I am loving this video because it is bringing out a lot of what I have heard, and stuff from other professionals who have been doing this for some time, and the disagreements between them.

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This obstruction test would be really cool to see with an L-shaped trace!

Looks great. As you said can get SMA connectors as cheap as 50c each but quality will decrease. They are still more consistent quality than BNC though, since they are SMD parts.

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Hi Hans. Thanks for the great videos, they perfectly match my style of learning and understanding! I had an idea about the coupling - not really sure how practical it would be in a real board though. On a 4 layer board could you alternate the loops between layers 1-2 and layers 3-4 to reduce coupling? Either by mounting components on both sides, or by some via trickery?

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Send me the checklist, please

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Hi, thanks for the videos. But what about the VCC plane. It is usually done in a iner layer for 4 layer PCB. It is a good practice to to this? Thnaks

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It’s nice and awesome to find these kinds of resources so well explained! Could you send me the checklist, please and thanks? :D

Can you increas the bandwith of that hyprid by desighning the PCB with more concentic conductive circle? Or could this hybrid be design as cone, so each additional circle could be in different plain. I see some wide band inductors that are design as cone shape to increas frequency responce. Wonder if that will work for hybride.

Would there be any advantage in going multilayer and using the outer layers as screening for the hybrid? Obviously the track widths would have to change to compensate for the extra ground plane etc.

I really like your videos. Thank you so much!!!!

Please send me the checklist! Thank you !

That's incredible and valuable content. Thanks. I would love to have your checklist as well. Cheers

Great! The videos are really helpful Hans. Please send me the checklist.

Could you suggest a loss calculator for a Grounded CPW PCB like you did in this video for a microstrip?

Very good process steps to get started on the RF path - RF is an endless learning journey. 3 other figure of merits to measure which I think are quite useful are Noise Figure, Return Loss and Two-Tone Intermodulation (IP3 or linearity). Noise figure can be measured easily and reasonably accurate without a noise source since it has some gain - gain method measurement. A few things, I think, that may impact the roll-off at >1 GHz: (1) Transition from microstrip to larger SMD pads increases capacitances. Some tricks arounds are to either use smaller SMD packages and/or use a stackup so that the microstrip lines are around the same size as the pads. (2) Also, FR4's Dk changes with frequency as it varies with frequency. If the 50R transmission line was designed for Dk at 100MHz, we can expect it to be less 50R at higher frequencies and eventually becoming more inductive. Cheers!

For drawing the ring with a given radius, do you take the inner size, the middle of the conductor, or the outer size? My guess would be the middle of the conductor but this may have some impact in the exact center frequency. Looking at the radius cs trace width this may be close to the difference you measure in the demo

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Another fantastic video. Thanks!

Hans; I haven't read it all yet, but the "book" has only 16 pages... As a "checklist", that's quite a bit, as a "book", a bit thin! Value, that's probably pretty good, for the cost of joining a mailing list.