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I followed the same procedure to create the new project, but i cant find the QPF file, V file and JSON files in the lab1 folder. please help me !!!

Can You Explain Me In Detail Which Code Are You Trying To Write For What Purpose?

Thanks!! Here from Brazil

Hello, i’m looking for analog ic design courses.Thank you

Thanks Rania !

From yahye hunter and muniir to liicaato

Can you convert the schematic to vhdl in quartus?

If you get invalid JTAG error, it must be due to .sof file. Go to top right section where it says SOF manager, then click on ... and locate the path for .sof file.

My input and output in testbench are missing. They do not appear in the Objects tab where I would be able to pull them over to the simulation tab. How can I solve it?

Thank you

I need your help how can I contact you?

thanks for every thing Madam! can you make a video for this question? Design a multiplier which calculates the product of two 4-bit numbers. Use half adder and/or full adder as basic building blocks and use other glue logic. Draw a schematic and verify it by simulation in Quartus. please I need your help! thanks again for your cooperation.

Congratulations

Hi, can you explain about 1/8 frequency divider using D flip flop?

Such a beautiful simulation to achieve thevenin's theorem...... Thank you so much 🤍

I have a very rudimentary fpga someone gave me an arduino Vidor. It has no buttons or leds but you can make hats for it. I would have to build the hat then define it in the hardware would I? My fpga has an atsamd51 processor with an Intel cyclone fpga chip along with a mini USB, hdmi ports along with Bluetooth and wifi modules. I am an hobbyist but have read books on logic and have built ttl based circuits like clocks, counters, phased lock loop, learned k mapping but not very well. Should I just buy a low-end xilinx with buttons and 4 digit 7 seg displays. I have all of this hardware and know how to make prototype boards that would connect to the arduino Vidor. Of course I'd have to learn how to connect and declare the modules properly. I'm just wondering your opinion as I've watched some of you're videos before and I know you're someone I can trust because of your experience. Thank you for the lessons ma'am.

Very good lesson by the way

Is this connected to an actual fpga?

Congratulations and so happy for you Professor Rania 👏👏👏

I'm using a DE0-nano board. When polling some registers in Signal tap for debugging, the register's name appears RED in color. I don't know what it signifies. If it appears in RED, then the register's value stays at zero. But, if I assign the register to an output port, its value changes to black and it functions as it is supposed to. But I have unwanted ports in the bdf now. Can anybody tell me what the RED color actually signifies and how can I fix it? Thanks in advance :)

very nice :)

"Our project was substantially delayed by many PID tuning issues" - Every Engineering Student to build a drone.

I don't have the modelsim_ase folder. on version 21.1 is it compulsory to use your directory pls what can I do

Thank you, hope you ll make more of FPGA tutorial !!

Thaaaaaanksss

You saved my ass, thanks a million

Hi Mam, Your QP lite vids are really helpful. Thank you.

Дякую

h5957d #von.ong

If you receive this error: "Error (199013): HDL output file name contains a non-existent directory path" try restore defaults to fix it: Simulation -> Simulation Settings -> Restore Defaults ->Save That worked for me!

Perfect exactly what I needed.

So useful! Thank you! By the way, I used the SOF manager to flash the sof file on the DE SoC board, not the device programmer but it will be the same...

There's absolutely no need to add resistor R4. Just leave it open circuited, run it and read out v0. That's your Vth. Then short circuit it and rerun for Isc (current through R3) and divide that into the previous v0 for Rth

What about the pin assignments ?!! and on the DE1-SOC if I am using an oscilloscope to check the signal where is the ground when all the pin are by directional

thank you so muchhhh, your help was great

gostei muito

melhor video

nota 10

top demais

Thank you

BE CULSEC représente l'enseeiht

Error (suppressible): (vsim-12110) The -novopt option has no effect on this product. -novopt

I have experiencing error during simulation

8:20 enable use

very helpful, thanks

I'm not able to find the working directory. I am a complete newbie and i dont know where to find directory .. or which directory

Very helpful, Thanks

very podre

This video was great, thank you!

How to add a pre existing file to this prjt hierarchy