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- Просмотров 67 358
ECE VIDEOS
Индия
Добавлен 12 ноя 2012
This channel is helpful for those who are studying Electronics and communication engineering and for those who are preparing for GATE exam.
Видео
Flash type adc
Просмотров 184 часа назад
#linearintegratedcircuits #lic #analogvlsi #analog #analoglab
Monostable multivibrator using opamp
Просмотров 227 часов назад
#linearintegratedcircuits #analog #analogvlsi #linear #lic
Wein Bridge oscillator using op amp
Просмотров 1914 часов назад
#lic #linearintegratedcircuits #linear #analog #analogvlsi
Square root carry select adder
Просмотров 1316 часов назад
Circuit analysis :ruclips.net/video/xfzkw-zm_cw/видео.html Aptitude:ruclips.net/video/hqi90ucWUkc/видео.html Digital image processing:ruclips.net/video/oG_ti59xNG8/видео.html Digital Electronics:ruclips.net/video/w-714YlpegI/видео.html
floating point representation
Просмотров 2119 часов назад
#digitalsystem #digitalsystemdesign #digitalelectronicslectures #digital #digitallogic #digitallogicdesign #digitallearning #digitalelectronic #digitalelectronics #floating
Essential hazards
Просмотров 2521 час назад
#digital #digitalelectronic #digitalelectronicslectures #digitalsystem #digitalsystemdesign #hazard #digitallogic #digitallogicdesign
dynamic hazards in digital circuits
Просмотров 61День назад
#digital #digitalelectronic #digitalelectronicslectures #digitalsystemdesign #digitalsystem #digitalsystems
design for testability in vlsi
Просмотров 23День назад
#vlsi #vlsidesign #vlsitechnology #vlsiprojects #vlsitraining #vlsijobs #testing #vlsiprojectcenters #dft
introduction to ASIC
Просмотров 12День назад
#vlsitechnology #vlsi #fpga #asics #vlsidesign #learnvlsi #vlsijobs #vlsiprojects #vlsiprojectcenters #vlsiexcellence
linear carry select adder
Просмотров 3814 дней назад
Tcritical =ktcarry for carry skip adder #vlsitechnology #vlsi #adderall #learnvlsi #vlsidesign #vlsiprojects #vlsiprojectcenters #vlsitraining #vlsiexcellence #vlsijobs
scan based design technique in VLSI DESIGN
Просмотров 9114 дней назад
scan based design technique in VLSI DESIGN
Design and simulate universal shift register using HDL
Просмотров 2014 дней назад
Design and simulate universal shift register using HDL
design ripple carry adder using block design
Просмотров 3814 дней назад
design ripple carry adder using block design
Design and simulate SR and T flipflop using HDL
Просмотров 2121 день назад
Design and simulate SR and T flipflop using HDL
Design and simulate Moore finite state machine using verilog HDL
Просмотров 2721 день назад
Design and simulate Moore finite state machine using verilog HDL
design and simulate D flipflop using HDL
Просмотров 1721 день назад
design and simulate D flipflop using HDL
design and simulate memories using HDL
Просмотров 1421 день назад
design and simulate memories using HDL
design and simulate Jk flipflop using hdl
Просмотров 2321 день назад
design and simulate Jk flipflop using hdl
design a 4 bit adder program using verilog hdl and implement it using basys 3
Просмотров 3621 день назад
design a 4 bit adder program using verilog hdl and implement it using basys 3
Design of a half adder using verilog HDL and implement it using Basys 3 board
Просмотров 4821 день назад
Design of a half adder using verilog HDL and implement it using Basys 3 board
implementation of Schmitt trigger circuit using mosfet
Просмотров 70Месяц назад
implementation of Schmitt trigger circuit using mosfet
Sir upload static hazard too
ruclips.net/video/IwXa00I2p74/видео.htmlsi=RewfjIrOmIHVZy8v
Sir please upload some more important question topics monday we have semester exam sir please. Just a humble request
Read DC transfer of nmos and cmos inverter, scaling of mosfet from unit 1.power consumption and problems on linear delay model, elmore constant, dynamic latch and register and pipelining, adders, multiplier and sram, asic types, soc and cmos fabrication
Read non ideal iv characteristics, static cmos and types of implementation, arbiter, time borrowing, metastable state, 1bit barrel shifter, classification of memory and it's difference, dft, controllabilty and Observability-2 marks
@@ECE_VIDEOS thank you so much sir
Very Very Thank you sir....❤
Most welcome
module halftest; reg a, b; wire sum, carry; halfadder uut( .a(a), .b(b),.sum(sum),.carry(carry) ); initial begin a = 0; b = 0; end always #10 a = ~a; always #5 b = ~b; endmodule Here is simple program for testbench
thank you😀😀😀😀😀
You are welcome!
please explain how to implement{ A(B+C)+CD}'
Check the video introduction to cmos logic
ruclips.net/video/d-hNaOlFGCc/видео.htmlsi=7JsIfPLCR7ZISZix
Thanku
Thank you sir it was very helpful ❤
Glad to hear that
Thank you sir❤
Most welcome
👏🔥 Great ❤️
Sir can you make a video on carry log shifter
Are you asking about logarithmic shifter?
@ECE_VIDEOS yes, Sir
Single and double are same concept say yes or no
No
Poor explanation
Noted
disagree, this is pretty good for how short it is
can you design dadda multiplier
amazing
Thanks
Sir please share that notes
Sir konjam please personal classes teach panna mudiyuma sir VLSi subject ku mattum please a kind humble request sir
Not possible
Sir intha notes konjam send panna mudiyum ma
In the first question the digital value is 50
யெஸ்
Why did we ignore the 2C?
Since it is between two transistors and is called diffusion capacitance
Super
Thanks
Super
Thanks
thank you so much sir for the video and clear explanation. How to contact you sir for teaching classes for doubts and getting your support for this subject
Sir put videos for static latches and register and for Dynamic also
Sure ma
ruclips.net/video/0IpyDloypjo/видео.htmlsi=Cg6qAxls8V_qurw7
Please Explain briefly
Logical effort of the inverter is 1 For nand gate is (n+2) /3 For nor gate is (2n+1) /3 Where n is number of input
Like wise u have it for xor and xnor gate
@@ECE_VIDEOS what is the formula for xor and xnor gates sir?
@@NagendraKrishna no formula
@@NagendraKrishna 4 for 2 input xor and 12 for 3 input xor gate
Hi
Sir. You're literally reading the contents in the slide. I was hoping for an explanation. Not satisfied!
Noted
Sir your phone please urgently i need your help for my analog on 24/6 please answer
the quality of the audio is bad
Noted
❤
Hi. I think there is an error in term 2 = QA'QBx' and not QA'QBx. Please verify Thanks
S, there is a mistake in Da value thank you for identifying it.
I have included it in the description box
You deserve a better microphone man the impact would be huge. Love the content.
Notes please
Very good
Sir teach in Tamil sir!!!
Sure I will
❤
Cbm 341 body area networks notes please
EXCELLENT PROF
Super sir super explanation 🎉
Share can you please share your mail id because I need your wearable devices ppt and notes to prepare for my semester exams!!!
Share can you please share your mail id because I need your wearable devices ppt and notes to prepare for my semester exams!!!
Share can you please share your mail id because I need your wearable devices ppt and notes to prepare for my semester exams!!!
Share can you please share your mail id because I need your wearable devices ppt and notes to prepare for my semester exams!!!
Share can you please share your mail id because I need your wearable devices ppt and notes to prepare for my semester exams!!!
Sir please upload other topics in wearable devices. Thank you.
Ok sure
Sir important question upload pls😢
Sir pls send notes
Keep doing sir.All new concepts👏👏👏
Thank you, I will
THANK YOU...I have been looking for a video like this for a very long time! I have the MF10 (in the +/- 5V mode) with a FIXED 100:1 oscillator/divider already added on. I wish to use MODE 3. I can now change the center frequency by varying the input square wave (50% duty cycle 5V TTL) from 1200Hz to 6000Hz. I wish to vary the output from 12Hz to 60Hz using ONLY the 100:1 clock ratio input. Can you please tell me what value resistors will work??? THANKS MUCH...THUMBS UP AND A SUBSCRIBE!!!!!!
Make R4=R2
www.ti.com/lit/pdf/snoa572
Very nice presentation
Tq for vedios sir