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Can u please explain SV verification environment for this ssme RAM module

Good explanation and presentation

sir , great video ===cleared all my doubts, very useful video

is "string" datatype is not supported by verilog ? I am trying this in vivado. Its giving error!

could you please explain what's the use of "comp" in the testench?

this is fifo ?

Sir do more videos based on sv

If we don't want the random values generated to be repeated rather we want unique random values for the same problem statement, then what could be the approach?

Could you please come up with some projects to highlight in profile for getting hired as verification engineer

Could you please come up with a session for projects on uvm to showcase in our profile for getting hired as design verification engineer.

sir what about other concept like task

thank you sir for this course ❤

Hey , whats is the course fee of asic verification profile and backend analoge design

confusing explanation

thanks for simplified and clear explanation

Sir , what about the fees

Nice explanation

Thank you

Why make mailbox static ???

Suggestion: Give some exercise questions at the end

Keep it up brother 💪👍 lots of love from guj bvn.

sir you are providing any live demo session now?

// Code your testbench here // or browse Examples module top; bit en; bit [2:0] data[$]; bit [2:0] data1[$]; initial begin for(int i=0;i<5;i++)begin data.push_back(i); data1.push_front(i); end $display("value is %0p",data); $display("value id %0p",data1); en=$random(); $display("value of en is %0d",en); if(en)begin while(data.size()!=0)begin $display("fifo : %0d",data.pop_front()); end end else begin while(data.size()!=0)begin $display("fifo : %0d",data.pop_back()); end end end endmodule

Nice

Is this course needed java

We are providing VLSI Front-End Design and Verification training (Verilog, System-Verilog, UVM, AMBA protocols) for fresher/professionals over weekends with job assurance, for more info can Whats-app @ 9997615007

module top; bit[3:0] data[3:0][7:0]; initial begin foreach(data[i,j])begin data[i][j] = $random; $display("data[%0d][%0d] = %b",i,j,data[i][j]); end end endmodule

module top; bit[0:3][7:0] data; initial begin foreach(data[i])begin data[i] = i+1; $display("data[%0d] = %m",i,data[i]); end end endmodule

Please release the next lecture, your explanation is very simple and easy to understand.

Thank you very much sir... Rarely in RUclips system verilog lecture is available and in hindi its very rarely... Thank you very much sir... I request you to kindly make a hindi playlist about system verilog all concepts..

Right sir... Hindi me full sv video banao sir sv me bahut confusion h

you can do more videos on sv concept very good explanation

Sir.. what is soc (system on chip)?? Can we assume mother board, on mother board there is a processor and Ram, does AXI protocol will helpful??

Hi in your 3rd example where you extended 2 classes, while printing you are saying it is overridden, then why is it printing from base base is displayed? It's overridden right?

Burst address calculation is (Start address / (len * size) ) * (len * size) Which means (len * size ) will cancel out each other. So is it always start address ?

What is cost of CHI Protocol

sir can you share constaints videos

Sir make videos on uvm protocol

Great sir

Thank you sir

Nice explanation with easy example

This tutorial is good start. you can also see this play list for further extending your understanding with the real life scenarios of AXI protocol: ruclips.net/p/PLMlIDhv1FUAVOrUjbnUyp8Ja9aIYObxec

Nice explaination

please explain upcasting and downcasting

Q1)How you take awburst=2? Q2)Upper boundary= lower wrap boundary+total no. Of transfers. In this total no of transfers i.e., awlen =4. U took 16.

We are providing VLSI Front-End Design and Verification training (Verilog, System-Verilog, UVM, AMBA protocols) for fresher/professionals over weekends with job assurance, for more info can visit on emicrobyte.com/ or Whatsapp @ 9997615007

Keep growing🤟🏻

Excellent explanation

Very good session 👍👍👍👍❤